专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050232287A1 High speed bus system that incorporates uni-directional point-to-point buses 失效
标题翻译：采用单向点对点总线的高速总线系统
公开(公告)号：US20050232287A1
公开(公告)日：2005-10-20
申请号：US11152213
申请日：2005-06-14
申请人： Raj Ramanujan , James Keller , William Samaras , John De Rosa , Robert Stewart
发明人： Raj Ramanujan , James Keller , William Samaras , John De Rosa , Robert Stewart
IPC分类号： G06F15/167 , G06F15/173 , H04L12/28 , H04L12/403
CPC分类号： H04L12/403 , G06F15/167 , G06F15/173 , H04L12/4625
摘要： An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.
摘要翻译：一种装置包括多个端口，其中每个端口适于耦合到设备。至少一个端口通过与设备的第一和第二单向，点对点通信链路连接。第一单向点对点通信链路将数据从设备传送到中央逻辑单元，第二单向点对点通信链路将数据从中央逻辑单元传送到设备。

2. 发明授权

US5278974A Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths 失效
标题翻译：用于动态调整数据传输定时以在具有不同带宽的计算机系统中均衡两个总线的带宽的方法和装置
公开(公告)号：US5278974A
公开(公告)日：1994-01-11
申请号：US445983
申请日：1989-12-04
申请人： Paul J. Lemmon , Raj Ramanujan , Jay C. Stickney
发明人： Paul J. Lemmon , Raj Ramanujan , Jay C. Stickney
IPC分类号： G06F13/14 , G06F13/16 , G06F13/40
CPC分类号： G06F13/1689 , G06F13/14 , G06F13/1684 , G06F13/4018
摘要： The bandwidth of a first bus and a second bus, unequal due to differences in protocol overheads and cycle times between the buses, are equalized without sacrificing any bandwidth on the lower bandwidth bus and without introducing any buffering in a control logic device. The control logic device equalizes the bandwidths of the buses by instructing a device coupled to the second bus to insert a partial dead bus cycle in a read transmission thereby dynamically adjusting read timing on the second bus when the second bus is heavily loaded.
摘要翻译：由于总线之间的协议开销和周期时间的差异而不平等的第一总线和第二总线的带宽被均衡，而不会牺牲低带宽总线上的任何带宽，而不会在控制逻辑器件中引入任何缓冲。控制逻辑设备通过指示耦合到第二总线的设备在读取传输中插入部分死区总线周期来均衡总线的带宽，从而当第二总线重负载时动态地调整第二总线上的读取定时。

3. 发明授权

US06807609B1 Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system 失效
标题翻译：在总线上交织读写操作，并最大限度地减少计算机系统内存模块的缓冲
公开(公告)号：US06807609B1
公开(公告)日：2004-10-19
申请号：US08067262
申请日：1993-05-25
申请人： Paul J. Lemmon , Raj Ramanujan
发明人： Paul J. Lemmon , Raj Ramanujan
IPC分类号： G06F1328
CPC分类号： G06F13/161
摘要： A computer system is adapted to transfer write data from a central processing unit to one of a plurality of memory modules in a memory array by transferring a block of write data to a memory control logic device. The memory control logic device transfers the block of data in a plurality of data bursts interspaced by a preselected number of bus cycles. During the interspaced preselected number of bus cycles, the memory control logic device sends pending read commands to an available memory module thereby overlapping read and write operations on the memory bus, thus, lowering memory read latency.
摘要翻译：计算机系统适于通过将写入数据块传送到存储器控制逻辑器件将写入数据从中央处理单元传送到存储器阵列中的多个存储器模块之一。存储器控制逻辑器件以预先选择的总线周期数间隔的多个数据突发传送数据块。在间隔预选数量的总线周期期间，存储器控制逻辑器件将待处理的读取命令发送到可用的存储器模块，从而在存储器总线上重叠读取和写入操作，从而降低存储器读取等待时间。

4. 发明申请

US20210051096A1 TECHNOLOGIES FOR QUALITY OF SERVICE BASED THROTTLING IN FABRIC ARCHITECTURES 有权
公开(公告)号：US20210051096A1
公开(公告)日：2021-02-18
申请号：US17086320
申请日：2020-10-30
申请人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj Ramanujan , Brian Slechta
发明人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj Ramanujan , Brian Slechta
IPC分类号： H04L12/725 , H04L12/803 , H04L12/933 , H04L12/825 , H04L12/931
摘要： Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.

5. 发明授权

US08838935B2 Apparatus, method, and system for implementing micro page tables 有权
标题翻译：用于实现微页表的装置，方法和系统
公开(公告)号：US08838935B2
公开(公告)日：2014-09-16
申请号：US12890585
申请日：2010-09-24
申请人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
发明人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
IPC分类号： G06F12/00 , G06F12/10 , G06F12/02
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.
摘要翻译：在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。

6. 发明授权

US07668997B2 High speed bus system that incorporates uni-directional point-to-point buses 失效
标题翻译：采用单向点对点总线的高速总线系统
公开(公告)号：US07668997B2
公开(公告)日：2010-02-23
申请号：US11152213
申请日：2005-06-14
申请人： Raj Ramanujan , James B. Keller , William A. Samaras , John DeRosa , Robert E. Stewart
发明人： Raj Ramanujan , James B. Keller , William A. Samaras , John DeRosa , Robert E. Stewart
IPC分类号： G06F12/00
CPC分类号： H04L12/403 , G06F15/167 , G06F15/173 , H04L12/4625
摘要： An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.
摘要翻译：一种装置包括多个端口，其中每个端口适于耦合到设备。至少一个端口通过与设备的第一和第二单向，点对点通信链路连接。第一单向点对点通信链路将数据从设备传送到中央逻辑单元，第二单向点对点通信链路将数据从中央逻辑单元传送到设备。

7. 发明授权

US5341491A Apparatus and method for ensuring that lock requests are serviced in a multiprocessor system 失效
标题翻译：用于确保在多处理器系统中服务锁定请求的装置和方法
公开(公告)号：US5341491A
公开(公告)日：1994-08-23
申请号：US141427
申请日：1993-10-22
申请人： Raj Ramanujan
发明人： Raj Ramanujan
IPC分类号： G06F9/46 , G06F12/14
CPC分类号： G06F9/524
摘要： A lockout avoidance circuit is provided for a plurality of nodes which generate lock requests for a shared resource such as a memory location. The circuit insures that lock requests are eventually satisfied. A lock queue includes a plurality of registers pipelined together. Lock requests only enter the lock queue if they are refused access to a shared resource a predetermined number of times. A first register is the head of the queue and the last register is the bottom of the queue. An enabling circuit allows the queue to store in the registers lock requests received from the different nodes in the order in which they are initially refused service. The enabling circuit operates the queue by pushing the stored lock requests toward the head of the queue each time the head entry in the queue is serviced. The lockout avoidance circuit is implemented at each level of the system wherein a lockout condition can occur.
摘要翻译：为多个节点提供闭锁避免电路，这些节点产生对诸如存储器位置的共享资源的锁定请求。电路确保最终满足锁定请求。锁定队列包括流水线化的多个寄存器。锁定请求仅在预定次数被拒绝访问共享资源时才进入锁定队列。第一个寄存器是队列的头，最后一个寄存器是队列的底部。启用电路允许队列以其最初被拒绝服务的顺序存储在寄存器中锁定从不同节点接收的请求。启用电路通过在每次服务队列中的头条目时将存储的锁定请求推送到队列的头部来操作队列。锁定避免电路在系统的每个级别实现，其中可能发生锁定状态。

8. 发明授权

US11343177B2 Technologies for quality of service based throttling in fabric architectures 有权
公开(公告)号：US11343177B2
公开(公告)日：2022-05-24
申请号：US17086320
申请日：2020-10-30
申请人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj Ramanujan , Brian Slechta
发明人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj Ramanujan , Brian Slechta
IPC分类号： H04L12/725 , H04L45/302 , H04L47/125 , H04L49/10 , H04L47/26 , H04L49/20
摘要： Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.

9. 发明申请

US20120079232A1 APPARATUS, METHOD, AND SYSTEM FOR IMPLEMENTING MICRO PAGE TABLES 有权
标题翻译：用于实施微型表格的装置，方法和系统
公开(公告)号：US20120079232A1
公开(公告)日：2012-03-29
申请号：US12890585
申请日：2010-09-24
申请人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
发明人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.
摘要翻译：公开了一种装置，方法，机器可读介质和系统。在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。微页表引擎允许TLB作为一个代理，确定二级存储器层次结构中的数据是在存储器的热区域还是在存储器的冷区域。当数据处于存储器的冷区域时，微页表引擎将数据读取到热存储器，然后将热存储器块推出到冷存储器区域。

10. 发明授权

US5263144A Method and apparatus for sharing data between processors in a computer system 失效
标题翻译：用于在计算机系统中的处理器之间共享数据的方法和装置
公开(公告)号：US5263144A
公开(公告)日：1993-11-16
申请号：US546508
申请日：1990-06-29
申请人： John H. Zurawski , Raj Ramanujan , John De Rosa
发明人： John H. Zurawski , Raj Ramanujan , John De Rosa
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0831
摘要： A cache coherency scheme in a multiprocessor computer system allows data sharing between caches at a fast rate. A new cache coherency state is introduced which allows a processor pair to more effectively share data and eliminate bus transfers thereby improving system throughput. The transfer of data is accomplished by the returning a portion of a preselected data block pursuant to either a read or a read for ownership request by a first one of the processors of the processor pair by the second processor of the processor pair. The ownership of the portion of the preselected data block is shared by the processor pair. Both processors set an indicator to denote that the preselected data block is an incomplete data block.
摘要翻译：多处理器计算机系统中的高速缓存一致性方案允许以高速率在高速缓存之间进行数据共享。引入了新的高速缓存一致性状态，允许处理器对更有效地共享数据并消除总线传输，从而提高系统吞吐量。通过处理器对的第二处理器由处理器对的第一处理器的所有权请求的读取或读取来返回预选数据块的一部分来实现数据的传送。预选数据块的部分的所有权由处理器对共享。两个处理器设置一个指示符，表示预先选择的数据块是不完整的数据块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式