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1. 发明授权

US08759872B2 Transistor with threshold voltage set notch and method of fabrication thereof 有权
标题翻译：具有阈值电压设置陷波器的晶体管及其制造方法
公开(公告)号：US08759872B2
公开(公告)日：2014-06-24
申请号：US12971955
申请日：2010-12-17
申请人： Reza Arghavani , Pushkar Ranade , Lucian Shifren , Scott E. Thompson , Catherine de Villeneuve
发明人： Reza Arghavani , Pushkar Ranade , Lucian Shifren , Scott E. Thompson , Catherine de Villeneuve
IPC分类号： H01L21/336 , H01L21/338
CPC分类号： H01L27/0921 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/823892 , H01L27/088 , H01L27/092 , H01L29/0653 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/365 , H01L29/4966 , H01L29/66537 , H01L29/6659 , H01L29/7833 , H01L29/7836
摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD, so that the body bias can be tuned separately from VT for a given device.
摘要翻译：其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT 更精确地设置。指示特征性缺口的新型掺杂物分布使得能够在精确范围内调整VT设置。可以通过适当选择金属来扩展该VT设定范围，使得在管芯上容纳非常宽范围的VT设置。与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。结果是能够独立地控制VT（具有低电平（VT））和VDD（VDD），从而使给定器件的体偏压可以与VT分开调谐。

2. 发明授权

US08173495B2 Semiconductor on insulator 有权
标题翻译：半导体绝缘体
公开(公告)号：US08173495B2
公开(公告)日：2012-05-08
申请号：US12911649
申请日：2010-10-25
申请人： Been-Yih Jin , Reza Arghavani , Robert Chau
发明人： Been-Yih Jin , Reza Arghavani , Robert Chau
IPC分类号： H01L21/00
CPC分类号： H01L21/02488 , H01L21/02532 , H01L21/7624 , H01L21/76254 , H01L21/76256
摘要： A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers.
摘要翻译：一种用于制造具有改善的载流子迁移率的相对薄的相对均匀的半导体层的方法和装置。在一个实施例中，在半导体衬底上形成晶格匹配的绝缘体层，并且在绝缘体层上形成晶格匹配的半导体层，以形成相对薄的相对均匀的半导体绝缘体设备。在该方法和装置的实施例中，可以使用能带特征来促进提取良好区域的少数载流子。

3. 发明授权

US07875932B2 Semiconductor on insulator apparatus 有权
标题翻译：绝缘体半导体器件
公开(公告)号：US07875932B2
公开(公告)日：2011-01-25
申请号：US12581794
申请日：2009-10-19
申请人： Been-Yih Jin , Reza Arghavani , Robert Chau
发明人： Been-Yih Jin , Reza Arghavani , Robert Chau
IPC分类号： H01L27/01
CPC分类号： H01L21/02488 , H01L21/02532 , H01L21/7624 , H01L21/76254 , H01L21/76256
摘要： A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers.
摘要翻译：一种用于制造具有改善的载流子迁移率的相对薄的相对均匀的半导体层的方法和装置。在一个实施例中，在半导体衬底上形成晶格匹配的绝缘体层，并且在绝缘体层上形成晶格匹配的半导体层，以形成相对薄的相对均匀的半导体绝缘体设备。在该方法和装置的实施例中，可以使用能带特征来促进提取良好区域的少数载流子。

4. 发明申请

US20080096356A1 Substrate Having Silicon Germanium Material and Stressed Silicon Nitride Layer 失效
标题翻译：具有硅锗材料和强化氮化硅层的基板
公开(公告)号：US20080096356A1
公开(公告)日：2008-04-24
申请号：US11924564
申请日：2007-10-25
申请人： Reza Arghavani
发明人： Reza Arghavani
IPC分类号： H01L21/336
CPC分类号： H01L21/0217 , H01L21/02271 , H01L21/3185 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L29/7848
摘要： A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate. The silicon germanium layer and stressed silicon nitride layer induce a stress in the doped silicon region of the substrate. In one version, the semiconductor device has a transistor with source and drain regions having the silicon germanium material, and the doped silicon region forms a channel that is configured to conduct charge between the source and drain regions. The stressed silicon nitride layer is formed over at least a portion of the channel, and can be a tensile or compressively stressed layer according the desired device characteristics.
摘要翻译：制造半导体器件的方法包括在衬底上提供具有掺杂硅区域的区域，以及在衬底上形成邻近该区域的硅锗材料。在衬底上的掺杂硅区域的至少一部分上形成应力氮化硅层。硅锗层和应力氮化硅层在衬底的掺杂硅区域中引起应力。在一个版本中，半导体器件具有晶体管，其源极和漏极区域具有硅锗材料，并且掺杂硅区域形成被配置为在源极和漏极区域之间传导电荷的通道。应力氮化硅层形成在通道的至少一部分上，并且可以是根据期望的器件特性的拉伸或压应力层。

5. 发明授权

US07323391B2 Substrate having silicon germanium material and stressed silicon nitride layer 有权
标题翻译：具有硅锗材料和应力氮化硅层的衬底
公开(公告)号：US07323391B2
公开(公告)日：2008-01-29
申请号：US11037684
申请日：2005-01-15
申请人： Reza Arghavani
发明人： Reza Arghavani
IPC分类号： H01L21/336
CPC分类号： H01L21/0217 , H01L21/02271 , H01L21/3185 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L29/7848
摘要： A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate. The silicon germanium layer and stressed silicon nitride layer induce a stress in the doped silicon region of the substrate. In one version, the semiconductor device has a transistor with source and drain regions having the silicon germanium material, and the doped silicon region forms a channel that is configured to conduct charge between the source and drain regions. The stressed silicon nitride layer is formed over at least a portion of the channel, and can be a tensile or compressively stressed layer according the desired device characteristics.
摘要翻译：制造半导体器件的方法包括在衬底上提供具有掺杂硅区域的区域，以及在衬底上形成邻近该区域的硅锗材料。在衬底上的掺杂硅区域的至少一部分上形成应力氮化硅层。硅锗层和应力氮化硅层在衬底的掺杂硅区域中引起应力。在一个版本中，半导体器件具有晶体管，其源极和漏极区域具有硅锗材料，并且掺杂硅区域形成被配置为在源极和漏极区域之间传导电荷的通道。应力氮化硅层形成在通道的至少一部分上，并且可以是根据期望的器件特性的拉伸或压应力层。

6. 发明授权

US07253123B2 Method for producing gate stack sidewall spacers 有权
标题翻译：栅堆叠侧墙的制造方法
公开(公告)号：US07253123B2
公开(公告)日：2007-08-07
申请号：US11032859
申请日：2005-01-10
申请人： Reza Arghavani , Michael Chiu Kwan , Li-Qun Xia , Kang Sub Yim
发明人： Reza Arghavani , Michael Chiu Kwan , Li-Qun Xia , Kang Sub Yim
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/4983 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/02329 , H01L21/0234 , H01L21/3148 , H01L21/31633 , H01L21/3185 , H01L29/6659
摘要： A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. The deposition is performed in a plasma enhanced chemical vapor deposition chamber and the deposition temperature is less than 450° C. The sidewall spacers so produced provide good capacity resistance, as well as excellent structural stability and hermeticity.
摘要翻译：一种用于在栅极堆叠上形成侧壁间隔物的方法，其通过在栅极结构上使用PECVD工艺沉积一层或多层含硅材料以产生具有约3.0至约5.0的总k值的间隔物。含硅材料可以是碳化硅，氧掺杂碳化硅，氮掺杂碳化硅，碳掺杂氮化硅，氮掺杂碳氧化碳或其组合。沉积在等离子体增强化学气相沉积室中进行，并且沉积温度低于450℃。如此制备的侧壁间隔物提供了良好的容量阻力以及良好的结构稳定性和气密性。

7. 发明申请

US20050266622A1 METHOD FOR FORMING A LOW THERMAL BUDGET SPACER 失效
标题翻译：形成低热预算间隔的方法
公开(公告)号：US20050266622A1
公开(公告)日：2005-12-01
申请号：US10854013
申请日：2004-05-25
申请人： Reza Arghavani , Ken MacWilliams , Hichem M'Saad
发明人： Reza Arghavani , Ken MacWilliams , Hichem M'Saad
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/336 , H01L21/44 , H01L21/8234
CPC分类号： H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02274 , H01L21/3145 , H01L21/31612 , H01L21/3185
摘要： A method of forming a sidewall spacer on a gate electrode of a metal oxide semiconductor device that includes striking a first plasma to form an oxide layer on a side of the gate electrode, where the first plasma is generated from a oxide gas that includes O3 and bis-(tertiarybutylamine)silane, and striking a second plasma to form a carbon-doped nitride layer on the oxide layer, where the second plasma may be generated from a nitride gas that includes NH3 and the bis-(tertiarybutylamine)silane. The first and second plasmas may be formed using plasma CVD and the bis-(tertiarybutylamine)silane flows uninterrupted between the striking of the first plasma and the striking of the second plasma.
摘要翻译：一种在金属氧化物半导体器件的栅电极上形成侧壁间隔物的方法，其包括冲击第一等离子体以在栅电极的一侧上形成氧化物层，其中第一等离子体由氧化物气体产生，和三（叔丁基胺）硅烷，并且冲击第二等离子体以在氧化物层上形成碳掺杂的氮化物层，其中第二等离子体可以由氮化物气体产生， 3和双 - （叔丁胺）硅烷。可以使用等离子体CVD形成第一和第二等离子体，并且双（叔丁胺）硅烷在第一等离子体的击打和第二等离子体的击打之间不间断地流动。

8. 发明申请

US20050239293A1 POST TREATMENT OF LOW K DIELECTRIC FILMS 有权
标题翻译：低K电介质膜的后处理
公开(公告)号：US20050239293A1
公开(公告)日：2005-10-27
申请号：US10830203
申请日：2004-04-21
申请人： Zhenjiang Cui , Josephine Chang , Alexandros Demos , Reza Arghavani , Derek Witty , Helen Armer , Girish Dixit , Hichem M'Saad
发明人： Zhenjiang Cui , Josephine Chang , Alexandros Demos , Reza Arghavani , Derek Witty , Helen Armer , Girish Dixit , Hichem M'Saad
IPC分类号： H01L21/314 , H01L21/316 , H01L21/4763 , H01L21/26 , H01L21/31 , H01L21/324 , H01L21/42 , H01L21/469 , H01L21/477
CPC分类号： H01L21/31633 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/02351
摘要： A method of depositing a low dielectric constant film on a substrate and post-treating the low dielectric constant film is provided. The post-treatment includes rapidly heating the low dielectric constant film to a desired high temperature and then rapidly cooling the low dielectric constant film such that the low dielectric constant film is exposed to the desired high temperature for about five seconds or less. In one aspect, the post-treatment also includes exposing the low dielectric constant film to an electron beam treatment and/or UV radiation.
摘要翻译：提供了一种在衬底上沉积低介电常数膜并对低介电常数膜进行后处理的方法。后处理包括将低介电常数膜快速加热到期望的高温，然后快速冷却低介电常数膜，使得低介电常数膜暴露于所需的高温约5秒或更短。一方面，后处理还包括将低介电常数膜暴露于电子束处理和/或UV辐射。

9. 发明授权

US06809017B2 Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication 失效
标题翻译：栅电极和高k电介质层的界面层及其制造方法
公开(公告)号：US06809017B2
公开(公告)日：2004-10-26
申请号：US10452088
申请日：2003-05-30
申请人： Reza Arghavani , Robert Chau , Mark Doczy , Brian Roberds
发明人： Reza Arghavani , Robert Chau , Mark Doczy , Brian Roberds
IPC分类号： H01L213205
CPC分类号： H01L21/28176 , H01L21/28035 , H01L21/28185 , H01L21/28194 , H01L21/31683 , H01L29/4925 , H01L29/517
摘要： Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.
摘要翻译：制造半导体器件的方法半导体器件包括衬底，形成在衬底上的高k栅介质层和沉积在高k栅介质层上的无氢栅电极，其中无氢栅电极是导电的。该方法包括在衬底上沉积高k栅极电介质层，在栅极电介质层上溅射栅电极并处理栅电极使得栅电极是导电的。

10. 发明授权

US06597046B1 Integrated circuit with multiple gate dielectric structures 有权
标题翻译：具有多栅绝缘结构的集成电路
公开(公告)号：US06597046B1
公开(公告)日：2003-07-22
申请号：US09378053
申请日：1999-08-20
申请人： Robert S. Chau , Reza Arghavani , Bruce Beattie
发明人： Robert S. Chau , Reza Arghavani , Bruce Beattie
IPC分类号： H01L2976
CPC分类号： H01L21/823462
摘要： An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface. In one embodiment the gate dielectric is an oxynitride formed by an N2 plasma; and the oxynitride has top surface nitrogen concentration that is higher than a bottom surface nitrogen concentration. In a further aspect of the present invention, an integrated circuit includes a plurality of IGFETs, wherein various ones of the plurality of IGFETs have different gate dielectric thicknesses and compositions. A method of forming IGFETs with different gate dielectric thicknesses and compositions, on a single integrated circuit, includes forming a first oxynitride layer, forming a masking layer, removing a portion of the first oxynitride layer, forming an oxide layer where the oxynitride was removed, and forming a plurality of gate electrodes, a first portion of the gate electrodes overlying the first oxynitride layer.
摘要翻译：集成电路包括绝缘栅场效应晶体管（IGFET），其具有栅极电介质层，其中栅极电介质中的氮浓度在栅极电极/栅极电介质界面处的第一浓度与栅极电介质/衬底界面处的第二浓度之间变化。在一个实施例中，栅极电介质是由N 2等离子体形成的氧氮化物; 氮氧化物的顶表面氮浓度高于底面氮浓度。在本发明的另一方面，集成电路包括多个IGFET，其中多个IGFET中的各种具有不同的栅介质厚度和组成。在单个集成电路上形成具有不同栅电介质厚度和组成的IGFET的方法包括形成第一氧氮化物层，形成掩模层，去除第一氮氧化物层的一部分，形成除去氧氮化物的氧化物层，以及形成多个栅电极，所述栅电极的覆盖所述第一氧氮化物层的第一部分。

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