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1. 发明专利

AU4910901A Methods for making nearly planar dielectric films in integrated circuits 未知
公开(公告)号：AU4910901A
公开(公告)日：2001-09-17
申请号：AU4910901
申请日：2001-03-07
申请人： MICRON TECHNOLOGY INC , WERNER JUENGLING
发明人： JUENGLING WERNER
IPC分类号： H01L21/3205 , H01L21/3105 , H01L21/316 , H01L21/768
摘要： In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers-the insulative layers sandwiched between layers of metal wiring-in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

2. 发明授权

US09190494B2 Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin 有权
标题翻译：包括翅片场效应晶体管的系统和器件均具有U形半导体鳍片
公开(公告)号：US09190494B2
公开(公告)日：2015-11-17
申请号：US12033799
申请日：2008-02-19
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/76 , H01L29/66 , H01L21/8234 , H01L27/088 , H01L27/108 , H01L29/78 , H01L21/336 , H01L21/76
CPC分类号： H01L29/66795 , H01L21/823431 , H01L27/0886 , H01L27/10876 , H01L27/10879 , H01L29/7851
摘要： Disclosed are methods, systems and devices, including a system, having a memory device. In some embodiments, the memory device includes a plurality of fin field-effect transistors disposed in rows, a plurality of insulating fins each disposed between the rows, and a plurality of memory elements each coupled to a terminal of a fin field-effect transistor among the plurality of fin field-effect transistors.
摘要翻译：公开了包括具有存储器装置的系统的方法，系统和装置。在一些实施例中，存储器件包括排列成行的多个鳍状场效应晶体管，各排设置在各行之间的多个绝缘鳍片，以及多个存储元件，每个存储器元件耦合到鳍状场效应晶体管的端子，多个鳍状场效应晶体管。

3. 发明授权

US08962401B2 Double gated 4F2 dram CHC cell and methods of fabricating the same 有权
标题翻译：双门控4F2二极管CHC电池及其制造方法
公开(公告)号：US08962401B2
公开(公告)日：2015-02-24
申请号：US13455956
申请日：2012-04-25
申请人： Werner Juengling , Howard C. Kirsch
发明人： Werner Juengling , Howard C. Kirsch
IPC分类号： H01L21/00 , H01L27/108 , H01L21/8234 , H01L27/088 , H01L29/10 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L29/0847 , H01L29/1037 , H01L29/4236 , H01L29/66484 , H01L29/66787 , H01L29/7855
摘要： A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.
摘要翻译：提供一种半导体器件，其包括在第一沟槽中形成有鳍状物的第一侧壁上的第一栅极和第二栅极的鳍片，其中第一栅极形成在第二栅极之上。该器件包括在第二沟槽中形成在鳍片的第二侧壁上的第三栅极和第四栅极，其中第三栅极形成在第四栅极之上。还包括制造和操作设备的方法。一种操作方法可以包括偏置第一栅极和第四栅极以产生穿过散热片的电流路径。

4. 发明授权

US08629483B2 Locally 2 sided CHC DRAM access transistor structure 有权
标题翻译：本地双面CHC DRAM存取晶体管结构
公开(公告)号：US08629483B2
公开(公告)日：2014-01-14
申请号：US13047774
申请日：2011-03-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10879 , H01L27/10826
摘要： A method for forming a DRAM memory with a two-sided transistor includes: providing a silicon finFET structure having at least two fins, and a trench between the fins; forming high ohmic gates on either side of the fins; forming a hole between each pair of high ohmic gates to enable connection between the pair of high ohmic gates; forming a gate on one side of the trench and underneath one of the pair of high ohmic gate; forming a layer of oxide over the gate; and depositing tungsten in the trench to form a thick layer of metal at the bottom to form a word line.
摘要翻译：用于形成具有双面晶体管的DRAM存储器的方法包括：提供具有至少两个散热片的硅finFET结构和鳍片之间的沟槽; 在翅片的两侧形成高欧姆门; 在每对高欧姆门之间形成一个孔，以使一对高欧姆门之间能够连接; 在沟槽的一侧形成栅极，并在该对高欧姆栅极之一的下面形成栅极; 在门上形成一层氧化物; 并且在沟槽中沉积钨以在底部形成厚的金属层以形成字线。

5. 发明授权

US08617953B2 Memory having a vertical access device 有权
标题翻译：内存具有垂直访问设备
公开(公告)号：US08617953B2
公开(公告)日：2013-12-31
申请号：US12966582
申请日：2010-12-13
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/336
CPC分类号： H01L27/10823 , H01L21/84 , H01L21/86 , H01L27/10876
摘要： Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on the side walls and the floor of the recess. A conductive film may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.
摘要翻译：公开了具有垂直存取装置的半导体存储器件。在一些实施例中，一种形成该装置的方法包括在半导体衬底中设置一凹槽，其包括一对相对的侧壁和在相对的侧壁之间延伸的底板。电介质层可以沉积在凹槽的侧壁和底板上。可以在电介质层上形成导电膜并加工成从凹槽的地板选择性地去除膜并从对置的侧壁去除至少一部分导电膜。

6. 发明授权

US08537608B2 Data cells with drivers and methods of making and operating the same 有权
公开(公告)号：US08537608B2
公开(公告)日：2013-09-17
申请号：US13612361
申请日：2012-09-12
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： G11C11/34
CPC分类号： G11C11/40 , H01L27/105 , H01L27/10814 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.

7. 发明授权

US08513722B2 Floating body cell structures, devices including same, and methods for forming same 有权
标题翻译：浮体细胞结构，包括其的装置及其形成方法
公开(公告)号：US08513722B2
公开(公告)日：2013-08-20
申请号：US12715843
申请日：2010-03-02
申请人： Sanh D. Tang , John K. Zahurak , Werner Juengling
发明人： Sanh D. Tang , John K. Zahurak , Werner Juengling
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10802 , H01L21/845 , H01L27/10826 , H01L27/10879 , H01L27/1211 , H01L29/4236 , H01L29/7841
摘要： Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.
摘要翻译：包括浮置体细胞结构，其包括布置在背栅上的浮体阵列阵列和与后门间隔开的浮体细胞的源区和漏区。浮体细胞可以各自包括体积的半导体材料，其具有在柱之间延伸的通道区域，其可以通过诸如U形沟槽的空隙分开。阵列的浮体电池可以电耦合到另一个栅极，另一个栅极可以设置在半导体材料的体积的侧壁上或其内的空隙中。还公开了形成浮体电池器件的方法。

8. 发明授权

US08416610B2 Systems and devices including local data lines and methods of using, making, and operating the same 有权
标题翻译：系统和设备包括本地数据线以及使用，制造和操作相同的方法
公开(公告)号：US08416610B2
公开(公告)日：2013-04-09
申请号：US12792557
申请日：2010-06-02
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： G11C11/24
CPC分类号： H01L28/91 , G11C7/02 , G11C11/4097 , G11C2213/71 , H01L27/0207 , H01L27/105 , H01L27/10817 , H01L27/10823 , H01L27/10826 , H01L27/10885 , H01L27/115 , H01L27/2436 , H01L29/7853
摘要： Disclosed are methods, systems and devices including local data lines. In some embodiments, the device includes a local data line connected to a plurality of access devices, at least a portion of a capacitor plate connected to the plurality of access devices, and a global data line connected to the local data line by the capacitor plate.
摘要翻译：公开了包括本地数据线的方法，系统和设备。在一些实施例中，设备包括连接到多个接入设备的本地数据线，连接到多个接入设备的电容器板的至少一部分，以及通过电容器板连接到本地数据线的全局数据线。

9. 发明申请

US20120256272A1 MEMORY DEVICE COMPRISING AN ARRAY PORTION AND A LOGIC PORTION 有权
标题翻译：包含阵列部分和逻辑部分的存储器件
公开(公告)号：US20120256272A1
公开(公告)日：2012-10-11
申请号：US13525730
申请日：2012-06-18
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/088
CPC分类号： H01L27/108 , H01L21/0337 , H01L27/088 , H01L27/10876 , H01L27/10894
摘要： In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.
摘要翻译：在本发明的实施例中，一种方法包括使用第一光刻掩模图案化半导体衬底的阵列部分中的第一多个半导体结构。该方法还包括使用第二光刻掩模在半导体衬底的逻辑部分上构图第二多个半导体结构。该方法还包括使用第二光刻掩模在第一多个半导体结构上图案化牺牲层。牺牲层与第二多个半导体结构同时被图案化。

10. 发明授权

US08278703B2 Cross-hair cell based floating body device 有权
标题翻译：基于跨毛细胞的浮体装置
公开(公告)号：US08278703B2
公开(公告)日：2012-10-02
申请号：US12702123
申请日：2010-02-08
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/66
CPC分类号： H01L29/7841 , H01L27/10802 , H01L27/10826 , H01L29/785
摘要： A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a fin having upper and lower doped regions. The upper doped regions may form a source and drain separated by a shallow trench formed in the fin. During formation of the fin, a hollow region may be formed underneath the shallow trench, isolating the source and drain. An oxide may be formed in the hollow region to form a floating body structure, wherein the source and drain are isolated from each other and the substrate formed below the fin. In some embodiments, independently bias gates may be formed adjacent to walls of the fin. In other embodiments, electrically coupled gates may be formed adjacent to the walls of the fin.
摘要翻译：公开了一种具有浮体结构的非平面晶体管及其制造方法。在某些实施例中，晶体管包括具有上和下掺杂区的鳍。上掺杂区域可以形成由在鳍片中形成的浅沟槽分离的源极和漏极。在翅片形成期间，可以在浅沟槽下方形成中空区域，隔离源极和漏极。可以在中空区域中形成氧化物以形成浮体结构，其中源极和漏极彼此隔离，并且形成在鳍下方的衬底。在一些实施例中，独立的偏置门可以邻近翅片的壁形成。在其他实施例中，电耦合栅极可以形成为邻近翅片的壁。

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