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1. 发明申请

WO2003048951A1 A SWITCHING I/O NODE FOR CONNECTION IN A MULTIPROCESSOR COMPUTER SYSTEM 审中-公开
标题翻译：用于在多处理器计算机系统中连接的切换I / O节点
公开(公告)号：WO2003048951A1
公开(公告)日：2003-06-12
申请号：PCT/US2002/028985
申请日：2002-09-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： GULICK, Dale, E.
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0024 , G06F2213/0026
摘要： A switching I/O node for connection in a multiprocessor computer system. An input/output node switch (400) includes a bridge unit (450) and a packet bus switch unit (430) implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus (455) and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link (435) and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link (401) and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link (402) in response to determining the destination each of the upstream packet transactions.
摘要翻译：用于在多处理器计算机系统中连接的交换I / O节点。输入/输出节点开关（400）包括在集成电路芯片上实现的桥接单元（450）和分组总线开关单元（430）。桥接单元可以从外围总线（455）接收多个外围事务，并且可以发送与多个外围事务相对应的多个上行分组事务。分组总线交换机可以在内部点对点分组总线链路（435）上接收上行分组事务，并且可以确定每个上行分组事务的目的地。分组总线交换机可以将上游分组事务中的选择的一个进一步路由到耦合到第一点对点分组总线链路（401）的第一处理器接口，并且将上游分组事务中的其它事务路由到耦合到响应于确定每个上游分组事务的目的地，第二点对点分组总线链路（402）。

2. 发明申请

WO1998018292A1 ARCHITECTURE FOR A UNIVERSAL SERIAL BUS-BASED PC SPEAKER CONTROLLER 审中-公开
标题翻译：通用串行总线型PC扬声器控制器的架构
公开(公告)号：WO1998018292A1
公开(公告)日：1998-04-30
申请号：PCT/US1997019478
申请日：1997-10-22
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , GULICK, Dale, E.
IPC分类号： H04R03/00
CPC分类号： H04R3/00
摘要： There is provided a novel powered loudspeaker implemented to be compatible with the USB specification. The powered speaker includes a speaker driven by a power amplifier coupled to a power supply. Both the amplifier and the power supply, in turn, are coupled to a USB controller. The controller is configured to provide USB functionality and compatibility. In addition, it provides a phase locked loop (PLL) for recovering a timer clock from the received data stream. The present invention further includes a function whereby the absence of data on the relevant channel is detected and the output to the speakers is muted in response thereto. A further circuit is provided that controls when the output to the speaker is turned on such that no clicks or pops occur at power-up or when the device or bus is not stable. In addition, tone control, including base and treble filters, volume control, and balance between left and right outputs (in a stereo version) are provided. Furthermore, power management functionality is provided. If the USB has been idle for a predetermined period of time, the system can place itself into a low power sleep mode, or the loudspeaker can be placed into a sleep mode via software from the host.
摘要翻译：提供了一种实现与USB规范兼容的新型有源扬声器。有源扬声器包括由耦合到电源的功率放大器驱动的扬声器。放大器和电源又连接到USB控制器。控制器配置为提供USB功能和兼容性。另外，它提供了一种用于从接收到的数据流中恢复定时器时钟的锁相环（PLL）。本发明还包括一个功能，其中检测到相关信道上的数据不存在，并且响应于此扬声器的输出被静音。提供另一电路，用于控制扬声器的输出何时被接通，使得在上电时或当设备或总线不稳定时不会发生点击或咔嗒声。此外，还提供了音调控制，包括基本和高音滤波器，音量控制以及左右输出之间的平衡（立体声版本）。此外，还提供电源管理功能。如果USB已经空闲了预定的时间段，则系统可以将自己置于低功率睡眠模式，或者可以通过来自主机的软件将扬声器置于睡眠模式。

3. 发明申请

WO2004099954A1 A COMPUTER SYSTEM INCLUDING A BUS BRIDGE FOR CONNECTION TO A SECURITY SERVICES PROCESSOR 审中-公开
标题翻译：包括用于连接到安全服务处理器的总线桥的计算机系统
公开(公告)号：WO2004099954A1
公开(公告)日：2004-11-18
申请号：PCT/US2004/000484
申请日：2004-01-09
申请人： ADVANCED MICRO DEVICES, INC. , GULICK, Dale, E. , STRONGIN, Geoffrey, S. , HEWITT, Larry, D.
发明人： GULICK, Dale, E. , STRONGIN, Geoffrey, S. , HEWITT, Larry, D.
IPC分类号： G06F1/00
CPC分类号： G06F21/74 , G06F21/85 , G06F2221/2105
摘要： A computer system (10, 20) including a bus bridge (121, 221, 321) for bridging transactions between a secure execution mode-capable processor (100A-B) and a security services processor (130). The bus bridge may include a transaction source detector (450), a configuration header (415) and control logic (416). The transaction source detector may receive a security initialization transaction performed as a result of execution of a security initialization instruction. Further, the transaction source detector may determine whether the secure execution mode-capable processor is a source of the security initialization transaction. The configuration header may provide storage of information associated with the security services processor. The control logic may determine whether the security services processor is coupled to the bus bridge via a non-enumerable, peripheral bus (135, 335). The control logic may also cause the configuration header to be accessible during a boot-up sequence in response to determining that the security services processor is coupled to the non-enumerable, peripheral bus.
摘要翻译：一种计算机系统（10,20），包括用于桥接安全执行模式处理器（100A-B）和安全服务处理器（130）之间的事务的总线桥（121,221,321）。总线桥可以包括事务源检测器（450），配置头（415）和控制逻辑（416）。事务源检测器可以接收由于执行安全初始化指令而执行的安全初始化事务。此外，事务源检测器可以确定具有安全执行模式的处理器是否是安全初始化事务的源。配置头可以提供与安全服务处理器相关联的信息的存储。控制逻辑可以确定安全服务处理器是否经由不可枚举的外围总线（135,335）耦合到总线桥。响应于确定安全服务处理器耦合到不可枚举的外围总线，控制逻辑还可以使配置头在启动序列期间可访问。

4. 发明申请

WO2004003757A2 DIRECT TRANSACTION MODE FOR PERIPHERAL DEVICES 审中-公开
标题翻译：用于外围设备的直接交互模式
公开(公告)号：WO2004003757A2
公开(公告)日：2004-01-08
申请号：PCT/US2003/020807
申请日：2003-06-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： GULICK, Dale, E.
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： A method and system for more directly reading from or writing to a peripheral device (8) coupled to a computer via a standard communication protocol (such as Universal Serial Bus (USB)) by bypassing portions of the standard communication technology. The host controller (4) monitors the status of a direct command queue (52) afterthe completion of each standard communication transaction. If a command is present in the direct command queue, the command is carried out before any standard communication transactions are performed. If no command is present in the direct command queue, a standard communication transaction is carried out. The relatively long latency encountered when accessing critical command and status registers via standard communication technology is thus avoided.
摘要翻译：一种用于通过绕过标准通信技术的一部分，通过标准通信协议（例如通用串行总线（USB））更直接地读取或写入耦合到计算机的外围设备（8）的方法和系统。主机控制器（4）在完成每个标准通信事务之后监视直接命令队列（52）的状态。如果直接命令队列中存在命令，则在执行任何标准通信事务之前执行命令。如果直接命令队列中没有命令，则执行标准通信事务。因此避免了通过标准通信技术访问关键命令和状态寄存器时遇到的相对较长的延迟。

5. 发明申请

WO2002093335A2 EXTERNAL LOCKING MECHANISM FOR PERSONAL COMPUTER MEMORY LOCATIONS 审中-公开
标题翻译：个人计算机存储位置的外部锁定机制
公开(公告)号：WO2002093335A2
公开(公告)日：2002-11-21
申请号：PCT/US2002/011930
申请日：2002-04-17
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WEBER, Frederick, D. , GULICK, Dale, E. , STRONGIN, Geoffrey, S.
IPC分类号： G06F1/00
CPC分类号： G06F21/74 , G06F21/53 , G06F21/575 , G06F21/72 , G06F21/79 , G06F21/85 , G06F2221/2107 , G06F2221/2141 , G06F2221/2147
摘要： A method and system for providing an external locking mechanism for memory locations. The memory includes a first plurality of storage locations configured with BIOS data and a second plurality of storage locations. The second plurality of storage locations includes a first plurality of blocks readable only in SMM and a second plurality of blocks readable in SMM and at least one operating mode other than SMM. The computer system includes a bus, a memory coupled to the bus, and a device coupled to access the memory over the bus. The memory includes a plurality of storage locations, divided into a plurality of memory units. The device includes one or more locks configured to control access to one or more of the plurality of memory units.
摘要翻译：一种用于为存储器位置提供外部锁定机构的方法和系统。存储器包括配置有BIOS数据的第一多个存储位置和第二多个存储位置。第二多个存储位置包括可在SMM中可读的第一多个块和在SMM中可读的第二多个块以及除了SMM之外的至少一个操作模式。计算机系统包括总线，耦合到总线的存储器以及耦合以通过总线访问存储器的设备。存储器包括被分成多个存储单元的多个存储位置。该设备包括配置成控制对多个存储器单元中的一个或多个的访问的一个或多个锁。

6. 发明申请

WO2003090074A2 INITIALIZATION OF A COMPUTER SYSTEM INCLUDING A SECURE EXECUTION MODE-CAPABLE PROCESSOR 审中-公开
标题翻译：包括安全执行模式处理器的计算机系统的初始化
公开(公告)号：WO2003090074A2
公开(公告)日：2003-10-30
申请号：PCT/US2003/011814
申请日：2003-04-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MCGRATH, Kevin, J. , STRONGIN, Geoffrey, S. , CHRISTIE, David, S. , HUGHES, William, A. , GULICK, Dale, E.
IPC分类号： G06F9/445
CPC分类号： G06F9/4403 , G06F12/1441 , G06F12/1458 , G06F12/1491
摘要： The initialization of a computer system (10) including a secure execution mode-capable processor (100) includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory (110). The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.
摘要翻译：包括安全执行模式的处理器（100）的计算机系统（10）的初始化包括将安全操作系统代码段加载程序存储到对应于系统存储器（110）内的特定地址范围的多个位置。该方法还包括执行安全初始化指令。执行安全初始化指令可能导致执行若干操作，包括发送包括特定地址范围的基地址的开始事务。此外，执行安全指令还可以引起执行另一操作，包括从系统存储器检索安全操作系统代码段加载器，并将安全操作系统代码段加载器发送为多个数据事务。

7. 发明申请

WO2003090052A3 A COMPUTER SYSTEM INCLUDING A SECURE EXECUTION MODE - CAPABLE CPU AND A SECURITY SERVICES PROCESSOR CONNECTED VIA A SECURE COMMUNICATION PATH 审中-公开
公开(公告)号：WO2003090052A3
公开(公告)日：2003-10-30
申请号：PCT/US2003/012659
申请日：2003-04-18
申请人： ADVANCED MICRO DEVICES INC.
发明人： MCGRATH, Kevin, J. , STRONGIN, Geoffrey, S. , GULICK, Dale, E. , HUGHES, William A. , CHRISTIE, David, S.
IPC分类号： G06F1/00
摘要： A computer system (10, 20) includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface (120, 220) coupled to the processor via an I/O link (225). The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor (130) coupled to the I/O interface via a peripheral bus (135). The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.

8. 发明申请

WO2003038646A3 MICROCOMPUTER BRIDGE ARCHITECTURE WITH AN EMBEDDED MICROCONTROLLER 审中-公开
公开(公告)号：WO2003038646A3
公开(公告)日：2003-05-08
申请号：PCT/US2002/028980
申请日：2002-09-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： GULICK, Dale, E.
IPC分类号： G06F15/78
摘要： An integrated circuit, a computer system, and a method of operating the computer system. The integrated circuit includes an internal bus and a microcontroller connected to the internal bus. The microcontroller is configured to master the internal bus. An Ethernet controller may also be coupled to the internal bus with a plurality of buffers coupled between the microcontroller and the Ethernet controller for buffering data between the microcontroller and the Ethernet controller. The Ethernet controller and the microcontroller are then configured to exchange data over the internal bus.

9. 发明申请

WO2002093335A3 EXTERNAL LOCKING MECHANISM FOR PERSONAL COMPUTER MEMORY LOCATIONS 审中-公开
公开(公告)号：WO2002093335A3
公开(公告)日：2002-11-21
申请号：PCT/US2002/011930
申请日：2002-04-17
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WEBER, Frederick, D. , GULICK, Dale, E. , STRONGIN, Geoffrey, S.
IPC分类号： G06F1/00
摘要： A method and system for providing an external locking mechanism for memory locations. The memory includes a first plurality of storage locations configured with BIOS data and a second plurality of storage locations. The second plurality of storage locations includes a first plurality of blocks readable only in SMM and a second plurality of blocks readable in SMM and at least one operating mode other than SMM. The computer system includes a bus, a memory coupled to the bus, and a device coupled to access the memory over the bus. The memory includes a plurality of storage locations, divided into a plurality of memory units. The device includes one or more locks configured to control access to one or more of the plurality of memory units.

10. 发明申请

WO2002019078A3 SYSTEM AND METHOD FOR MONITORING AND CONTROLLING A POWER MANAGEABLE RESOURCE 审中-公开
公开(公告)号：WO2002019078A3
公开(公告)日：2002-03-07
申请号：PCT/US2001/015122
申请日：2001-05-09
申请人： ADVANCED MICRO DEVICES, INC.
发明人： GULICK, Dale, E.
IPC分类号： G06F1/32
摘要： A system and method for monitoring and controlling a power-manageable resource (16). In one embodiment, a power manageable resource, such as a bus in a computer system, may be shareable among a number of power-manageable devices (21A-21C). A resource monitor (25) may also be coupled to the power-manageable resource. The resource monitor may be configured to monitor the devices coupled to the power manageable resource. More specifically, the functions of the resource monitor may include monitoring the active/inactive state of each of the attached devices. The resource monitor may be configured to cause the sharable resource to be powered down if it is determined that all the attached devices are in an inactive state.

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