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1. 发明授权

US07216310B2 Design method and system for optimum performance in integrated circuits that use power management 有权
标题翻译：使用电源管理的集成电路中的最佳性能设计方法和系统
公开(公告)号：US07216310B2
公开(公告)日：2007-05-08
申请号：US10993815
申请日：2004-11-19
申请人： Amitava Chatterjee , David Barry Scott , Theodore W. Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
发明人： Amitava Chatterjee , David Barry Scott , Theodore W. Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
IPC分类号： G06F17/50 , G11C5/14 , H03K3/01 , G05F1/10
CPC分类号： G06F17/505
摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
摘要翻译：本发明提供一种设计电路的方法（100）。该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

2. 发明申请

US20050149887A1 Design method and system for optimum performance in integrated circuits that use power management 有权
标题翻译：使用电源管理的集成电路中的最佳性能设计方法和系统
公开(公告)号：US20050149887A1
公开(公告)日：2005-07-07
申请号：US10993815
申请日：2004-11-19
申请人： Amitava Chatterjee , David Scott , Theodore Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
发明人： Amitava Chatterjee , David Scott , Theodore Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
摘要翻译：本发明提供一种设计电路的方法（100）。该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

3. 发明授权

US06855984B1 Process to reduce gate edge drain leakage in semiconductor devices 有权
标题翻译：降低半导体器件漏极漏极的工艺
公开(公告)号：US06855984B1
公开(公告)日：2005-02-15
申请号：US10697510
申请日：2003-10-30
申请人： Zhiqiang Wu , Shaoping Tang , Song Zhao
发明人： Zhiqiang Wu , Shaoping Tang , Song Zhao
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823842 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/6656 , H01L29/7833
摘要： The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.
摘要翻译：本发明在NMOS器件中形成有源区之后采用n型注入的无掩模，覆盖式注入。结果，注入的n型掺杂剂抵消了强p型HALO或凹坑区域的部分，从而产生了更平滑的掺杂物分布或从有源区域的一部分到沟道的转变。然而，橡皮布注入在相对较低的能量下进行，以便不会将活性区的一个或多个其它部分显着地改变到该装置的其它部分。

4. 发明申请

US20060024910A1 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) 有权
标题翻译：在CMOS技术中使用浅沟槽隔离（STI）来设计反向窄宽度效应（INWE）的方法，
公开(公告)号：US20060024910A1
公开(公告)日：2006-02-02
申请号：US10899664
申请日：2004-07-27
申请人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
发明人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/823878
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).
摘要翻译：公开了一种形成隔离结构的方法（200），并且包括在与隔离区域相关联的半导体本体（214）中形成隔离沟槽，并用植入物掩模材料（216）填充隔离沟槽的底部。在其底部填充有注入掩模材料之后，在隔离沟槽（218）中进行成角度的离子注入，从而在半导体本体中形成阈值电压补偿区域。随后，隔离沟槽填充有电介质材料（220）。

5. 发明授权

US06794730B2 High performance PNP bipolar device fully compatible with CMOS process 有权
标题翻译：高性能PNP双极器件完全兼容CMOS工艺
公开(公告)号：US06794730B2
公开(公告)日：2004-09-21
申请号：US10028002
申请日：2001-12-20
申请人： Youngmin Kim , Shaoping Tang , Seetharaman Sridhar , Amitava Chatterjee
发明人： Youngmin Kim , Shaoping Tang , Seetharaman Sridhar , Amitava Chatterjee
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.
摘要翻译：通过减小p阱注入的深度以增加发射极中的载流子浓度并使发射极结更深以增加发射极中的少数寿命，形成pnp双极结型晶体管，其具有改善的发射极效率。形成高增益BJT，而不对工艺流程添加掩模步骤。在优选实施例中，使用覆盖的高能量硼注入来抑制SRAM中的隔离泄漏。

6. 发明授权

US07045436B2 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) 有权
公开(公告)号：US07045436B2
公开(公告)日：2006-05-16
申请号：US10899664
申请日：2004-07-27
申请人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
发明人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
IPC分类号： H01L21/762
CPC分类号： H01L21/76237 , H01L21/823878
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).

7. 发明授权

US07795085B2 Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs 有权
标题翻译：有意义的口袋阴影以补偿SRAM中交叉扩散的影响
公开(公告)号：US07795085B2
公开(公告)日：2010-09-14
申请号：US11451264
申请日：2006-06-12
申请人： Jong Shik Yoon , Amitava Chatterjee , Kayvan Sadra , Shaoping Tang
发明人： Jong Shik Yoon , Amitava Chatterjee , Kayvan Sadra , Shaoping Tang
IPC分类号： H01L21/8238
CPC分类号： H01L27/1104 , H01L27/11
摘要： Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.
摘要翻译：公开了用于形成具有对称注入的有源区并在其中减少的交叉扩散的SRAM单元的方法。一种方法包括图案化覆盖在半导体衬底上的抗蚀剂层，以形成对称地位于电池的有源区的相对侧上的抗蚀剂结构，使用第一注入使用抗蚀剂结构作为注入掩模注入一种或多种掺杂物种，衬底，相对于第一注入约180度，以及使用抗蚀剂结构作为植入掩模，用第二注入将一种或多种掺杂剂物质注入到半导体衬底中。还公开了执行对称角度注入的方法，以在电池内提供减小的交叉扩散，包括在电池的有源区域的相对侧上图案化等间隔的抗蚀剂结构，以同样地遮蔽横向相对的第一和第二倾斜植入物。

8. 发明授权

US06933203B2 Methods for improving well to well isolation 有权
标题翻译：改善井良好隔离的方法
公开(公告)号：US06933203B2
公开(公告)日：2005-08-23
申请号：US10299525
申请日：2002-11-19
申请人： Zhiqiang Wu , Shaoping Tang , Jau-Yuann Yang
发明人： Zhiqiang Wu , Shaoping Tang , Jau-Yuann Yang
IPC分类号： H01L21/761 , H01L21/762 , H01L21/8234 , H01L21/00
CPC分类号： H01L21/76237 , H01L21/761 , H01L21/823481
摘要： Methods are provided for forming wells in a semiconductor wafer, in which p-wells and n-wells are formed in a substrate, and first p-type dopants are implanted into n-well regions while an n-well mask remains over the wafer to selectively decrease a substrate resistivity in the n-well regions beneath the n-wells. A subsequent blanket implantation provides second p-type dopants into isolation regions of the substrate beneath isolation structures, where the first and second p-type dopants improve well to well isolation without addition of extra masks to the fabrication process.
摘要翻译：提供了用于在半导体晶片中形成阱的方法，其中在衬底中形成p阱和n阱，并且将第一p型掺杂剂注入到n阱区域中，同时n阱掩模保留在晶片上，选择性地降低n阱下面的n阱区中的衬底电阻率。随后的覆盖植入在隔离结构下方的衬底的隔离区域中提供第二p型掺杂剂，其中第一和第二p型掺杂剂改善了良好的良好隔离，而没有向制造工艺添加额外的掩模。

9. 发明申请

US20070176263A1 Nwell to nwell isolation 有权
标题翻译：保持隔离
公开(公告)号：US20070176263A1
公开(公告)日：2007-08-02
申请号：US11343695
申请日：2006-01-31
申请人： Shaoping Tang , Zhiqiang Wu
发明人： Shaoping Tang , Zhiqiang Wu
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/266 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892
摘要： Multiple blanket implantations of one or more p type dopants into a semiconductor substrate are performed to facilitate isolation between nwell regions subsequently formed in the substrate. The blanket implantations are performed through isolation regions in the substrate so that the p type dopants are implanted to depths sufficient to separate the nwell regions. This increased concentration of p type dopants helps to mitigate leakage between the nwell regions as the nwell regions are brought closer together to increase packing densities.
摘要翻译：执行一个或多个p型掺杂剂到半导体衬底中的多次覆盖注入，以便于随后在衬底中形成的n阱区之间的隔离。通过衬底中的隔离区域进行覆盖注入，使得p型掺杂剂被植入足以分离nwell区域的深度。这种增加的p型掺杂剂的浓度有助于减轻nwell区域之间的泄漏，因为nwell区域靠近在一起以增加包装密度。

10. 发明授权

US07662690B2 Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate adjacent wells 有权
标题翻译：制备半导体衬底的方法，该半导体衬底利用在隔离区域下的多个植入物隔离相邻的孔
公开(公告)号：US07662690B2
公开(公告)日：2010-02-16
申请号：US11343695
申请日：2006-01-31
申请人： Shaoping Tang , Zhiqiang Wu
发明人： Shaoping Tang , Zhiqiang Wu
IPC分类号： H01L21/761
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/266 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892
摘要： Multiple blanket implantations of one or more p type dopants into a semiconductor substrate are performed to facilitate isolation between nwell regions subsequently formed in the substrate. The blanket implantations are performed through isolation regions in the substrate so that the p type dopants are implanted to depths sufficient to separate the nwell regions. This increased concentration of p type dopants helps to mitigate leakage between the nwell regions as the nwell regions are brought closer together to increase packing densities.
摘要翻译：执行一个或多个p型掺杂剂到半导体衬底中的多次覆盖注入，以便于随后在衬底中形成的n阱区之间的隔离。通过衬底中的隔离区域进行覆盖注入，使得p型掺杂剂被植入足以分离nwell区域的深度。这种增加的p型掺杂剂的浓度有助于减轻nwell区域之间的泄漏，因为nwell区域靠近在一起以增加包装密度。

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