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    • 2. 发明申请
    • Intelligent Pigments and Plastics
    • 智能颜料和塑料
    • US20120276647A1
    • 2012-11-01
    • US13502268
    • 2010-10-14
    • Andrew MillsPauline GrosshansGraham Skinner
    • Andrew MillsPauline GrosshansGraham Skinner
    • G01N21/78G01N21/76
    • G01N31/223C08K5/105C08K5/46C08K9/04G01N21/78G01N2021/7786G01N2021/7793G01N2021/7796C08L23/06
    • A chemical indicator comprises a particulate inorganic substrate, and at least one reactive dye or ink coated on and/or impregnated within the particulate inorganic substrate. Coating and/or impregnating at least one reactive dye or ink on or within a particulate inorganic substrate improves the storage stability and/or thermal stability of the at least one reactive dye or ink, which typically comprises relatively unstable compounds. This allows the present indicators to be incorporated into thermoplastic polymer materials and processed conventionally while maintaining the efficacy and stability of the new indicators. The indicators provide simple, reliable, and cost effective detection means for detecting analytes such as ammonia, carbon dioxide, and oxygen, and may find use in applications such as food packaging and medical applications.
    • 化学指示剂包括无机颗粒颗粒和至少一种涂覆在和/或浸渍在无机颗粒颗粒内的活性染料或油墨。 在颗粒状无机基材上或其内部涂覆和/或浸渍至少一种活性染料或油墨改善了至少一种活性染料或油墨的储存稳定性和/或热稳定性,其通常包含相对不稳定的化合物。 这允许将本指标并入热塑性聚合物材料中,并且在保持新指标的功效和稳定性的同时进行常规加工。 这些指标为检测分析物(如氨,二氧化碳和氧气)提供了简单,可靠和经济的检测手段,可用于食品包装和医疗应用等应用。
    • 3. 发明授权
    • Method and apparatus for supporting physical layer link-suspend operation between network nodes
    • 用于支持网络节点之间的物理层链路挂起操作的方法和装置
    • US06795450B1
    • 2004-09-21
    • US09676040
    • 2000-09-28
    • Andrew MillsRalph Andersson
    • Andrew MillsRalph Andersson
    • H04L1266
    • H04L12/12H04L69/24Y02D50/20Y02D50/40
    • A link-suspend operation between network nodes in a point-to-point data communications link is presented. Individual network links will have a full power operational mode for supporting full high-bandwidth communication, and a low power “link-suspend” (LS) operational mode for temporary operation when only limited communication is occurring. The communications link is maintained, while cycling transmitter power on and off during idle periods with a duty cycle that substantially reduces physical layer device (PHY) power, using LSPs. LS mode may be negotiated by advertising capabilities between two network devices. Thus, PHYs at either end of a link can notify the other of the capability to support a LS mode of operation and can negotiate parameters for communications using the LS mode. Further, transmitting and receiving continuous idles, valid data frames, and Wake-on LAN (WOL) packets is supported. Similarly, notification of “wake-up” schemes and detection of suspended WOL network device is supported.
    • 提出了点对点数据通信链路中网络节点之间的链接挂起操作。 单个网络链路将具有全功率运行模式,用于支持全高带宽通信,并且仅在有限通信发生时进行临时操作的低功耗“链路暂停”(LS)操作模式。 保持通信链路,同时在空闲周期期间使发射机的电源开启和关闭,同时使用LSP大大降低物理层设备(PHY)功率的占空比。 LS模式可以通过两个网络设备之间的广告能力进行协商。 因此,链路任一端的PHY可以通知另一个支持LS操作模式的能力,并且可以使用LS模式协商用于通信的参数。 此外,支持发送和接收连续空闲,有效数据帧和唤醒LAN(WOL)分组。 同样,支持“唤醒”方案的通知和挂起的WOL网络设备的检测。
    • 10. 发明授权
    • Central processing unit including APX and DSP cores which receives and
processes APX and DSP instructions
    • 中央处理单元包括接收和处理APX和DSP指令的APX和DSP内核
    • US6032247A
    • 2000-02-29
    • US969865
    • 1997-11-14
    • Saf AsgharAndrew Mills
    • Saf AsgharAndrew Mills
    • G06F9/30G06F9/318G06F9/38G06F15/78G06F15/00
    • G06F9/3836G06F15/7857G06F9/30174G06F9/30189G06F9/382G06F9/3822G06F9/384G06F9/3855G06F9/3857G06F9/3885
    • A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the processor mode bits indicate that X86 instructions in the instruction memory do not implement a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. In a second embodiment, the CPU receives sequences of instructions comprising X86 instructions and DSP instructions. The processor mode register is written with one or more processor mode bits to indicate whether an instruction sequence comprises X86 or DSP instructions, and the instructions are routed to the X86 core or to the DSP core accordingly.
    • 包括通用CPU组件(例如X86内核)的CPU或微处理器,还包括DSP内核。 在第一实施例中,CPU接收诸如X86指令的通用指令,其中某些X86指令序列实现DSP功能。 CPU包括处理器模式寄存器,其被写入一个或多个处理器模式位以指示指令序列是否实现DSP功能。 CPU还包括智能DSP功能解码器或预处理器,它检查处理器模式位,并确定DSP功能是否正在执行。 如果通过指令序列实现DSP功能,则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 如果处理器模式位指示指令存储器中的X86指令不实现DSP类型功能,则将操作码提供给当前现有技术计算机系统中发生的X86内核。 在第二实施例中,CPU接收包括X86指令和DSP指令的指令序列。 处理器模式寄存器用一个或多个处理器模式位写入,以指示指令序列是否包括X86或DSP指令,并将指令相应地路由到X86内核或DSP内核。