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1. 发明申请

US20210103662A1 TECHNIQUES FOR RESTRICTED DEPLOYMENT OF TARGETED PROCESSOR FIRMWARE UPDATES 有权
公开(公告)号：US20210103662A1
公开(公告)日：2021-04-08
申请号：US17127122
申请日：2020-12-18
申请人： Chinmay Ashok , Vasudevan Srinivasan , Atanas K. Iwanow , Martin G. Dixon , Scott J. Cape , Scott Bobholz , David T. Mayo , Vinila Rose , Lorie Wigle , Jason Kennedy
发明人： Chinmay Ashok , Vasudevan Srinivasan , Atanas K. Iwanow , Martin G. Dixon , Scott J. Cape , Scott Bobholz , David T. Mayo , Vinila Rose , Lorie Wigle , Jason Kennedy
IPC分类号： G06F21/57 , G06F8/65 , G06F21/44 , G06F21/10
摘要： Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.

2. 发明授权

US07380174B2 Variable writing through a fixed programming interface 有权
标题翻译：通过固定编程接口进行变量写入
公开(公告)号：US07380174B2
公开(公告)日：2008-05-27
申请号：US10952463
申请日：2004-09-28
申请人： David T. Mayo , Bradley G. Culter , Dennis Mazur
发明人： David T. Mayo , Bradley G. Culter , Dennis Mazur
IPC分类号： G06F11/00
CPC分类号： G06F11/0751 , G06F11/0724
摘要： Embodiments include writing a first data value to a validation variable through a fixed programming interface, where the validation variable includes multiple fields that correspond to multiple fields within a persistent variable. Contents of the validation variable are subsequently read through the fixed programming interface. When the validation variable contents include one or more differences from the first data value, one or more errors are identified.
摘要翻译：实施例包括通过固定编程接口向验证变量写入第一数据值，其中验证变量包括对应于持久变量内的多个字段的多个字段。验证变量的内容随后通过固定编程接口读取。当验证变量内容包括与第一数据值的一个或多个差异时，识别出一个或多个错误。

3. 发明授权

US06920516B2 Anti-starvation interrupt protocol 有权
标题翻译：抗饥饿中断协议
公开(公告)号：US06920516B2
公开(公告)日：2005-07-19
申请号：US09944516
申请日：2001-08-31
申请人： David W. Hartwell , Samuel H. Duncan , David T. Mayo , David J. Golden
发明人： David W. Hartwell , Samuel H. Duncan , David T. Mayo , David J. Golden
IPC分类号： G06F13/24 , G06F13/40 , H03K5/19
CPC分类号： H03K5/19 , G06F13/24 , G06F13/4081 , G06F2213/2402
摘要： An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction. If it does, the interrupt controller issues a write transaction having a higher priority to the second CSR. In response, the processor copies all of the pending interrupts from the first CSR into the memory subsystem, thereby freeing up the first CSR to accept additional write transactions.
摘要翻译：提供了一种用于避免多处理器计算机系统中的活动锁定的反饥饿中断协议。至少一个处理器被配置为包括第一和第二控制状态寄存器（CSR）。第一个CSR缓冲器由处理器接收到的中断信息，而第二个CSR跟踪中断的优先级。当中断控制器接收到中断时，它会在处理器发出写入事务给第一个CSR。如果第一个CSR有空间接受写入事务，则处理器返回确认，而如果第一个CSR已经满，则处理器返回一个无确认。响应于无应答，中断控制器增加中断饥饿计数器，并检查计数器是否超过阈值。如果没有，则中断控制器等待预设时间并转发写入事务。如果是这样，中断控制器向第二个CSR发出具有较高优先级的写入事务。作为响应，处理器将来自第一CSR的所有待处理中断复制到存储器子系统中，从而释放第一个CSR以接受额外的写事务。

4. 发明授权

US5652861A System for interleaving memory modules and banks 失效
标题翻译：用于交织存储器模块和存储体的系统
公开(公告)号：US5652861A
公开(公告)日：1997-07-29
申请号：US687692
申请日：1996-07-26
申请人： David T. Mayo , David W. Hartwell , Hansel A. Collins
发明人： David T. Mayo , David W. Hartwell , Hansel A. Collins
IPC分类号： G06F12/06
CPC分类号： G06F12/0607 , G06F12/0653
摘要： A memory system for a digital computer has first and second memory modules having differing numbers of independently-accessible banks and unlike capacities. The digital computer also has an addressing arrangement that employs horizontal stacking for interleaving together the banks of both the first and second memory modules, such that the first memory module is interleaved to a first level and the second memory module to a second, different level. The invention also embraces a method of interleaving the memory system employing horizontal stacking. In usual applications, horizontal stacking permits the memory system to be interleaved to a higher level than that achieved by conventional vertical stacking schemes.
摘要翻译：用于数字计算机的存储器系统具有第一和第二存储器模块，其具有不同数量的可独立存取的存储体并且与容量不同。数字计算机还具有寻址布置，其采用水平堆叠来将第一和第二存储器模块的组交错在一起，使得第一存储器模块被交织到第一级，而第二存储器模块交错到第二级别。本发明还包括使用水平堆叠来交织存储器系统的方法。在通常的应用中，水平堆叠允许存储器系统被交错到比常规垂直堆叠方案实现的更高的水平。

5. 发明授权

US07099978B2 Method and system of completing pending I/O device reads in a multiple-processor computer system 有权
标题翻译：在多处理器计算机系统中完成未完成的I / O设备读取的方法和系统
公开(公告)号：US07099978B2
公开(公告)日：2006-08-29
申请号：US10662782
申请日：2003-09-15
申请人： Samuel H. Duncan , Andrej Kocev , David T. Mayo
发明人： Samuel H. Duncan , Andrej Kocev , David T. Mayo
IPC分类号： G06F13/32 , G06F13/24
CPC分类号： G06F13/24 , G06F2213/0024
摘要： A method and system for completing pending I/O device reads by periodically stalling the issuance of I/O device accesses by a program in a multiple-processor computer system.
摘要翻译：一种用于通过在多处理器计算机系统中的程序周期性地停止I / O设备访问的发布来完成未完成的I / O设备读取的方法和系统。

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