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    • 3. 发明授权
    • Anti-starvation interrupt protocol
    • 抗饥饿中断协议
    • US06920516B2
    • 2005-07-19
    • US09944516
    • 2001-08-31
    • David W. HartwellSamuel H. DuncanDavid T. MayoDavid J. Golden
    • David W. HartwellSamuel H. DuncanDavid T. MayoDavid J. Golden
    • G06F13/24G06F13/40H03K5/19
    • H03K5/19G06F13/24G06F13/4081G06F2213/2402
    • An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction. If it does, the interrupt controller issues a write transaction having a higher priority to the second CSR. In response, the processor copies all of the pending interrupts from the first CSR into the memory subsystem, thereby freeing up the first CSR to accept additional write transactions.
    • 提供了一种用于避免多处理器计算机系统中的活动锁定的反饥饿中断协议。 至少一个处理器被配置为包括第一和第二控制状态寄存器(CSR)。 第一个CSR缓冲器由处理器接收到的中断信息,而第二个CSR跟踪中断的优先级。 当中断控制器接收到中断时,它会在处理器发出写入事务给第一个CSR。 如果第一个CSR有空间接受写入事务,则处理器返回确认,而如果第一个CSR已经满,则处理器返回一个无确认。 响应于无应答,中断控制器增加中断饥饿计数器,并检查计数器是否超过阈值。 如果没有,则中断控制器等待预设时间并转发写入事务。 如果是这样,中断控制器向第二个CSR发出具有较高优先级的写入事务。 作为响应,处理器将来自第一CSR的所有待处理中断复制到存储器子系统中,从而释放第一个CSR以接受额外的写事务。
    • 4. 发明授权
    • System for interleaving memory modules and banks
    • 用于交织存储器模块和存储体的系统
    • US5652861A
    • 1997-07-29
    • US687692
    • 1996-07-26
    • David T. MayoDavid W. HartwellHansel A. Collins
    • David T. MayoDavid W. HartwellHansel A. Collins
    • G06F12/06
    • G06F12/0607G06F12/0653
    • A memory system for a digital computer has first and second memory modules having differing numbers of independently-accessible banks and unlike capacities. The digital computer also has an addressing arrangement that employs horizontal stacking for interleaving together the banks of both the first and second memory modules, such that the first memory module is interleaved to a first level and the second memory module to a second, different level. The invention also embraces a method of interleaving the memory system employing horizontal stacking. In usual applications, horizontal stacking permits the memory system to be interleaved to a higher level than that achieved by conventional vertical stacking schemes.
    • 用于数字计算机的存储器系统具有第一和第二存储器模块,其具有不同数量的可独立存取的存储体并且与容量不同。 数字计算机还具有寻址布置,其采用水平堆叠来将第一和第二存储器模块的组交错在一起,使得第一存储器模块被交织到第一级,而第二存储器模块交错到第二级别。 本发明还包括使用水平堆叠来交织存储器系统的方法。 在通常的应用中,水平堆叠允许存储器系统被交错到比常规垂直堆叠方案实现的更高的水平。