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1. 发明申请

US20140344553A1 Gathering and Scattering Multiple Data Elements 审中-公开
标题翻译：收集和散布多个数据元素
公开(公告)号：US20140344553A1
公开(公告)日：2014-11-20
申请号：US13898189
申请日：2013-05-20
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译：根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

2. 发明申请

US20180129506A1 GATHERING AND SCATTERING MULTIPLE DATA ELEMENTS 审中-公开
公开(公告)号：US20180129506A1
公开(公告)日：2018-05-10
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

3. 发明申请

US20110153983A1 Gathering and Scattering Multiple Data Elements 有权
标题翻译：收集和散布多个数据元素
公开(公告)号：US20110153983A1
公开(公告)日：2011-06-23
申请号：US12644440
申请日：2009-12-22
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F15/76 , G06F9/06 , G06F12/08
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3865
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译：根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

4. 发明授权

US08447962B2 Gathering and scattering multiple data elements 有权
标题翻译：收集和散布多个数据元素
公开(公告)号：US08447962B2
公开(公告)日：2013-05-21
申请号：US12644440
申请日：2009-12-22
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3865
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译：根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

5. 发明授权

US10114651B2 Gathering and scattering multiple data elements 有权
公开(公告)号：US10114651B2
公开(公告)日：2018-10-30
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/00 , G06F12/08 , G06F9/38 , G06F9/30
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

6. 发明申请

US20140344552A1 PROVIDING STATUS OF A PROCESSING DEVICE WITH PERIODIC SYNCHRONIZATION POINT IN INSTRUCTION TRACING SYSTEM 有权
标题翻译：在指令跟踪系统中提供具有定期同步点的处理设备的状态
公开(公告)号：US20140344552A1
公开(公告)日：2014-11-20
申请号：US13895595
申请日：2013-05-16
申请人： Frank Binns , Matthew C. Merten , Mayank Bomb , Beeman C. Strong , Peter Lachner , Jason W. Brandt , Itamar Kazachinsky , Ofer Levy , MD A. Rahman
发明人： Frank Binns , Matthew C. Merten , Mayank Bomb , Beeman C. Strong , Peter Lachner , Jason W. Brandt , Itamar Kazachinsky , Ofer Levy , MD A. Rahman
IPC分类号： G06F9/30
CPC分类号： G06F11/3636 , G06F11/3024 , G06F11/3055 , G06F11/3476 , G06F11/348 , G06F2201/865
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.
摘要翻译：根据本文公开的实施例，提供了用于在指令跟踪系统中提供具有周期性同步点的处理设备的状态的系统和方法。例如，该方法可以包括基于分组日志中的唯一字节模式生成边界分组。边界包提供了分组解码的起始点。该方法还可以包括基于处理器的状态信息生成多个状态分组。当输出到分组日志中时，多个状态分组遵循边界分组。

7. 发明授权

US09189360B2 Processor that records tracing data in non contiguous system memory slices 有权
标题翻译：在不连续的系统内存片中记录跟踪数据的处理器
公开(公告)号：US09189360B2
公开(公告)日：2015-11-17
申请号：US13918940
申请日：2013-06-15
申请人： Beeman C. Strong , Jason W. Brandt , Tsvika Kurts , Peter Lachner , Itamar Kazachinsky , Stephen J. Robinson , Peggy J. Irelan
发明人： Beeman C. Strong , Jason W. Brandt , Tsvika Kurts , Peter Lachner , Itamar Kazachinsky , Stephen J. Robinson , Peggy J. Irelan
IPC分类号： G06F12/00 , G06F11/34 , G06F11/36 , G06F11/32 , G06F12/02 , G06F12/06
CPC分类号： G06F11/34 , G06F9/30 , G06F11/323 , G06F11/3466 , G06F11/3476 , G06F11/3636 , G06F11/3664 , G06F11/3668 , G06F12/023 , G06F12/06
摘要： A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.
摘要翻译：描述了涉及从系统存储器中的目录表引用第一信息的方法。第一信息包括要存储第一跟踪数据的系统存储器的第一片段的位置信息和大小信息。该方法还包括跟踪存储在系统存储器的第一片中的跟踪数据量，并将该量与尺寸信息进行比较。该方法还包括在系统存储器的第一片填充之前，参考来自系统存储器中的目录表的第二信息，其中第二信息包括系统存储器的第二片的位置信息和大小信息，其中第二追踪数据是被存储。第一个片段与系统内存的第二个片段不连续。

8. 发明授权

US09003375B2 Optional logging of debug activities in a real time instruction tracing log 有权
标题翻译：在实时指令跟踪日志中选择性地记录调试活动
公开(公告)号：US09003375B2
公开(公告)日：2015-04-07
申请号：US13993477
申请日：2011-12-30
申请人： Jason W. Brandt , Peter Lachner , Huy V. Nguyen , Jonathan J. Tyler
发明人： Jason W. Brandt , Peter Lachner , Huy V. Nguyen , Jonathan J. Tyler
IPC分类号： G06F11/36 , G06F9/44 , G06F11/34 , G06F9/06 , G06F9/30
CPC分类号： G06F11/3466 , G06F9/06 , G06F9/30 , G06F11/34 , G06F11/3476 , G06F11/3495 , G06F11/36 , G06F11/3636 , G06F2201/805
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing optional logging of debug activities in a real time instruction tracing log. For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets to a debug log describing the instruction tracing; means for initiating an alternative mode of execution within the integrated circuit; and means for suppressing indication of entering the alternative mode of execution. Additional and alternative means may be implemented for selectively causing an integrated circuit to operate in accordance with an invisible trace mode or a visible trace mode upon transition to the alternative mode of execution.
摘要翻译：根据本文公开的实施例，提供了用于在实时指令跟踪日志中实现可选日志记录调试活动的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括集成电路，该集成电路具有用于对由跟踪的应用，模式或代码区域的指令进行指令跟踪的装置，因为该指令由集成电路执行; 用于将多个分组生成到描述所述指令跟踪的调试日志的装置; 用于在集成电路内启动替代执行模式的装置; 以及用于抑制进入替代执行模式的指示的装置。可以实现附加和替代手段，用于在转换到替代执行模式时，根据不可见的跟踪模式或可视跟踪模式选择性地使集成电路进行操作。

9. 发明申请

US20140372987A1 Processor That Records Tracing Data In Non Contiguous System Memory Slices 有权
标题翻译：在非连续系统内存片中记录跟踪数据的处理器
公开(公告)号：US20140372987A1
公开(公告)日：2014-12-18
申请号：US13918940
申请日：2013-06-15
申请人： Beeman C. Strong , Jason W. Brandt , Tsvika Kurts , Peter Lachner , Itamar Kazachinsky , Stephen J. Robinson , Peggy J. Irelan
发明人： Beeman C. Strong , Jason W. Brandt , Tsvika Kurts , Peter Lachner , Itamar Kazachinsky , Stephen J. Robinson , Peggy J. Irelan
IPC分类号： G06F11/34
CPC分类号： G06F11/34 , G06F9/30 , G06F11/323 , G06F11/3466 , G06F11/3476 , G06F11/3636 , G06F11/3664 , G06F11/3668 , G06F12/023 , G06F12/06
摘要： A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.
摘要翻译：描述了涉及从系统存储器中的目录表引用第一信息的方法。第一信息包括要存储第一跟踪数据的系统存储器的第一片段的位置信息和大小信息。该方法还包括跟踪存储在系统存储器的第一片中的跟踪数据量，并将该量与尺寸信息进行比较。该方法还包括在系统存储器的第一片填充之前，参考来自系统存储器中的目录表的第二信息，其中第二信息包括系统存储器的第二片的位置信息和大小信息，其中第二追踪数据是被存储。第一个片段与系统内存的第二个片段不连续。

10. 发明申请

US20130263093A1 OPTIONAL LOGGING OF DEBUG ACTIVITIES IN A REAL TIME INSTRUCTION TRACING LOG 有权
标题翻译：实时追踪日志中调试活动的可选登录
公开(公告)号：US20130263093A1
公开(公告)日：2013-10-03
申请号：US13993477
申请日：2011-12-30
申请人： Jason W. Brandt , Peter Lachner , Huy V. Nguyen , Jonathan J. Tyler
发明人： Jason W. Brandt , Peter Lachner , Huy V. Nguyen , Jonathan J. Tyler
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F9/06 , G06F9/30 , G06F11/34 , G06F11/3476 , G06F11/3495 , G06F11/36 , G06F11/3636 , G06F2201/805
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing optional logging of debug activities in a real time instruction tracing log. For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets to a debug log describing the instruction tracing; means for initiating an alternative mode of execution within the integrated circuit; and means for suppressing indication of entering the alternative mode of execution. Additional and alternative means may be implemented for selectively causing an integrated circuit to operate in accordance with an invisible trace mode or a visible trace mode upon transition to the alternative mode of execution.
摘要翻译：根据本文公开的实施例，提供了用于在实时指令跟踪日志中实现可选日志记录调试活动的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括集成电路，该集成电路具有用于对由跟踪的应用，模式或代码区域的指令进行指令跟踪的装置，因为该指令由集成电路执行; 用于将多个分组生成到描述所述指令跟踪的调试日志的装置; 用于在集成电路内启动替代执行模式的装置; 以及用于抑制进入替代执行模式的指示的装置。可以实现附加和替代手段，用于在转换到替代执行模式时，根据不可见的跟踪模式或可视跟踪模式选择性地使集成电路进行操作。

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