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    • 5. 发明授权
    • Adaptive transmit rate control scheduler
    • 自适应传输速率控制调度器
    • US6011798A
    • 2000-01-04
    • US912260
    • 1997-08-15
    • Gary McAlpine
    • Gary McAlpine
    • H04L12/56H04Q11/04H04L12/28
    • H04L12/5601H04L2012/5651H04L2012/5679
    • An adaptive rate control scheduler multiplexes virtual circuit data stream elements for transmission onto a network from a network node. The rate control scheduler is an adaptive circuit that utilizes a schedule table (having multiple time windows) and a set of virtual circuit (VC) specific rate control parameters to supply a transmit controller with a stream of tokens (each of which represents an active VC). The order in which tokens are supplied to the transmit controller is based upon their respective time slot locations in the schedule table. Each time a token is processed by the transmit scheduler, a target time for the next processing of the VC represented by the token is calculated, based upon the stored VC-specific parameters. The token is then inserted into the schedule table in the nearest available time slot to the calculated target time. Included in the calculation of the next target time for a particular token is a gain function based upon an accumulated error value for the associated VC. The accumulated error represents error introduced into the VC's data stream by the scheduling process.
    • 自适应速率控制调度器从网络节点复用用于传输到网络的虚拟电路数据流元件。 速率控制调度器是利用调度表(具有多个时间窗口)和一组虚拟电路(VC)特定速率控制参数的自适应电路,以向发送控制器提供令牌流(每个代表活动VC )。 将令牌提供给发送控制器的顺序基于其在调度表中的相应时隙位置。 每次由发送调度器处理令牌时,基于存储的VC特定参数来计算用于由令牌表示的VC的下一个处理的目标时间。 然后将令牌插入到计划目标时间的最近可用时隙中的计划表中。 在特定令牌的下一个目标时间的计算中包括基于相关VC的累积误差值的增益函数。 累积误差表示通过调度过程引入VC数据流的错误。
    • 6. 发明申请
    • Directional and priority based flow control mechanism between nodes
    • 节点之间的基于定向和优先级的流控制机制
    • US20060053117A1
    • 2006-03-09
    • US10957895
    • 2004-09-30
    • Gary McAlpineTanmay GuptaManoj Wadekar
    • Gary McAlpineTanmay GuptaManoj Wadekar
    • G06F17/30
    • H04L47/20H04L47/10H04L47/125H04L47/2441H04L47/26H04L47/30H04L47/6215
    • A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.
    • 节点使用发射队列的二维阵列来存储要从节点发送到另一个节点的帧。 阵列的大小由另一个节点可以一旦从节点接收到的帧转发的方向的数量以及可能与帧相关联的优先级的数量来控制。 基于方向和优先级将发送队列彼此区分开。 发射机将发送队列出队的帧发送到另一个节点。 控制发送队列的控制逻辑从另一个节点接收指示,否则其他节点正在任何方向上经历业务拥塞,以及控制逻辑要控制从对应于发送队列的帧出队的帧的优先级 到另一个节点遇到交通拥堵的方向。
    • 7. 发明授权
    • Directional and priority based flow control mechanism between nodes
    • 节点之间的基于定向和优先级的流控制机制
    • US07457245B2
    • 2008-11-25
    • US10957895
    • 2004-09-30
    • Gary McAlpineTanmay GuptaManoj K. Wadekar
    • Gary McAlpineTanmay GuptaManoj K. Wadekar
    • H04J1/16
    • H04L47/20H04L47/10H04L47/125H04L47/2441H04L47/26H04L47/30H04L47/6215
    • A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.
    • 节点使用发射队列的二维阵列来存储要从节点发送到另一个节点的帧。 阵列的大小由另一个节点可以一旦从节点接收到的帧转发的方向的数量以及可能与帧相关联的优先级的数量来控制。 基于方向和优先级将发送队列彼此区分开。 发射机将发送队列出队的帧发送到另一个节点。 控制发送队列的控制逻辑从另一个节点接收指示,否则其他节点正在任何方向上经历业务拥塞,以及控制逻辑要控制从对应于发送队列的帧出队的帧的优先级 到另一个节点遇到交通拥堵的方向。
    • 9. 发明授权
    • Data transfer system and method of operation thereof
    • 数据传输系统及其操作方法
    • US4837785A
    • 1989-06-06
    • US504150
    • 1983-06-14
    • Gary McAlpine
    • Gary McAlpine
    • G06F13/38G06F13/364G06F13/42
    • G06F13/364G06F13/4291
    • A data transfer system with improved data transfer efficiency is provided. The system consists of a data interchange bus having two data transfer signal paths, an address signal path, and a plurality of control signal paths. Data interchange adapters and memory interchange adapters are coupled to the bus for transferring data thereover. A data interchange adapter transfers data on the first data signal path to another data interchange adapter or to a memory interchange adapter for storage in a memory device. A memory interchange adapter transfers data obtained from a memory device on the second data signal path to a data interchange adapter. Data transfers on the two data signal paths may be made simultaneously. Data transfers on both data signal paths are made synchronously. When an interchange adapter has data to be transferred, it provides an access request signal to a data interchange bus controller which intermittently latches all outstanding access requests, examines them, and produces a sequence of grant signals, each satisfying one of the latched request signals. When the sequence is completed, the controller again latches the access requests which had been raised during the prior latching and granting procedure. The data interchange adapter is further provided with the capability of coupling to two other data buses while coupled to the data interchange bus and includes interface and control circuitry for routing signals between any two of the three buses.
    • 提供了具有改进的数据传输效率的数据传输系统。 该系统由具有两个数据传输信号路径,地址信号路径和多个控制信号路径的数据交换总线组成。 数据交换适配器和存储器交换适配器耦合到总线,用于在其上传输数据。 数据交换适配器将第一数据信号路径上的数据传送到另一个数据交换适配器或存储器交换适配器,以存储在存储设备中。 存储器交换适配器将从第二数据信号路径上的存储器件获得的数据传送到数据交换适配器。 两个数据信号路径上的数据传输可以同时进行。 两个数据信号路径上的数据传输是同步进行的。 当交换适配器具有要传送的数据时,它向数据交换总线控制器提供访问请求信号,该数据交换总线控制器间歇地锁存所有未完成的访问请求,检查它们,并且产生一系列授权信号,每个请求信号满足锁存的请求信号之一。 当序列完成时,控制器再次锁存在先前锁存和授权过程中已经提出的访问请求。 数据交换适配器还具有耦合到两个数据总线同时耦合到数据交换总线的能力,并且包括用于在三个总线中的任何两个之间路由信号的接口和控制电路。