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1. 发明专利

GB2519259B Apparatus and method for reducing the flushing time of a cache 未知
公开(公告)号：GB2519259B
公开(公告)日：2020-08-19
申请号：GB201501454
申请日：2013-06-27
申请人： INTEL CORP , JAIDEEP MOSES , RAVISHANKAR IYER , RAMESH ILLIKKAL , SADAGOPAN SRINIVASAN
发明人： JAIDEEP MOSES , RAVISHANKAR IYER , RAMESH ILLIKKAL , SADAGOPAN SRINIVASAN
IPC分类号： G06F12/08
摘要： A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.

2. 发明申请

US20220012592A1 METHODS AND APPARATUS TO PERFORM WEIGHT AND ACTIVATION COMPRESSION AND DECOMPRESSION 有权
公开(公告)号：US20220012592A1
公开(公告)日：2022-01-13
申请号：US17483693
申请日：2021-09-23
申请人： Nilesh Jain , Menachem Adelman , Raanan Sade , Ravishankar Iyer , Rajesh Poornachandran , Yash Akhauri
发明人： Nilesh Jain , Menachem Adelman , Raanan Sade , Ravishankar Iyer , Rajesh Poornachandran , Yash Akhauri
IPC分类号： G06N3/08 , H03M7/30 , G06F17/16
摘要： Methods, apparatus, systems, and articles of manufacture to perform weight and activation compression and decompression are disclosed. An example apparatus includes memory, instructions in the apparatus, and processor circuitry to execute the instructions to execute a compression operation to obtain compressed data corresponding to weights in a weight matrix, and determine meta-data associated with the weight matrix, a first portion of the meta-data indicative of whether the weight matrix is compressed, a second portion of the meta-data indicative of a cache size of the compressed data, and a third portion of the meta-data indicative of the compression operation executed to obtain the compressed data.

3. 发明申请

US20170173455A1 MULTI-PLAYER GAME INPUT WITH DETECTION OF CONTEXT AND PHYSICAL OBJECT USAGE 审中-公开
公开(公告)号：US20170173455A1
公开(公告)日：2017-06-22
申请号：US14978054
申请日：2015-12-22
申请人： Daniel P. Sheil , Glen J. Anderson , Mark R. Francis , Ravishankar Iyer , Yevgeniy Y. Yarmosh
发明人： Daniel P. Sheil , Glen J. Anderson , Mark R. Francis , Ravishankar Iyer , Yevgeniy Y. Yarmosh
IPC分类号： A63F13/235 , A63F13/215 , A63F13/211 , A63F13/213 , A63F13/35 , A63F13/69
CPC分类号： A63F13/235 , A63F13/211 , A63F13/213 , A63F13/215 , A63F13/35 , A63F13/67 , A63F13/69 , A63F13/87 , A63F13/98
摘要： Systems, apparatuses and methods may provide for determining a state of a multi-player game and identifying a user communication associated with the multi-player game. Additionally, an outbound communication may be generated based on the user communication and the state of the multi-player game. In one example, generating the outbound communication includes conducting a weighted selection of one or more of a recipient, a content or an audio effect of the outbound communication based on the state.

4. 发明申请

US20140258685A1 Using Reduced Instruction Set Cores 审中-公开
标题翻译：使用精简指令集内核
公开(公告)号：US20140258685A1
公开(公告)日：2014-09-11
申请号：US13992856
申请日：2011-12-30
申请人： Srihari Makineni , Steven R. King , Alexander Redkin , Joshua B. Fryman , Ravishankar Iyer , Pavel S. Smirnov , Dmitry Gusev , Dmitri Pavlov
发明人： Srihari Makineni , Steven R. King , Alexander Redkin , Joshua B. Fryman , Ravishankar Iyer , Pavel S. Smirnov , Dmitry Gusev , Dmitri Pavlov
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F1/3234 , G06F9/30181 , G06F9/30196 , G06F9/3891
摘要： A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
摘要翻译：处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。因此，在一些实施例中，可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。不支持的指令可以以其他更节能的方式处理，使得包括部分核心的整体处理器可以完全向后兼容。

5. 发明申请

US20140201281A1 Social Network for Mobile Nodes 有权
标题翻译：移动节点社交网络
公开(公告)号：US20140201281A1
公开(公告)日：2014-07-17
申请号：US13993144
申请日：2011-12-30
申请人： Omesh Tickoo , Ravishankar Iyer
发明人： Omesh Tickoo , Ravishankar Iyer
IPC分类号： H04W4/00
CPC分类号： H04W4/003 , H04W4/023 , H04W4/21 , H04W4/60 , H04W8/18
摘要： A social network may be established between mobile nodes using a wireless connection. Establishing the social network may be based on an estimated time duration of the wireless connection. In one or more embodiments, establishing the social network may also be based on a similarity of interests among of users of the nodes.
摘要翻译：可以使用无线连接在移动节点之间建立社交网络。建立社交网络可以基于无线连接的估计持续时间。在一个或多个实施例中，建立社交网络也可以基于节点的用户之间的兴趣的相似性。

6. 发明申请

US20140188470A1 FLEXIBLE ARCHITECTURE FOR ACOUSTIC SIGNAL PROCESSING ENGINE 有权
标题翻译：声学信号处理发动机的灵活结构
公开(公告)号：US20140188470A1
公开(公告)日：2014-07-03
申请号：US13732329
申请日：2012-12-31
申请人： Jenny Chang , Michael E. Deisher , Ravishankar Iyer
发明人： Jenny Chang , Michael E. Deisher , Ravishankar Iyer
IPC分类号： G10L15/28
CPC分类号： G10L15/14
摘要： A disclosed speech processor includes a front end to receive a speech input and generate a feature vector indicative of a portion of the speech input and a Gaussian mixture (GMM) circuit to receive the feature vector, model any one of a plurality of GMM speech recognition algorithms, and generate a GMM score for the feature vector based on the GMM speech recognition algorithm modeled. In at least one embodiment, the GMM circuit includes a common compute block to generate feature a vector sum indicative of a weighted sum of differences squares between the feature vector and a mixture component of the GMM speech recognition algorithm. In at least one embodiment, the GMM speech recognition algorithm being modeled includes a plurality of Gaussian mixture components and the common compute block is operable to generate feature vector scores corresponding to each of the plurality of mixture components.
摘要翻译：公开的语音处理器包括前端，用于接收语音输入并产生指示语音输入的一部分的特征向量和接收特征向量的高斯混合（GMM）电路，模拟多个GMM语音识别中的任何一个算法，并且基于建模的GMM语音识别算法为特征向量生成GMM得分。在至少一个实施例中，GMM电路包括公共计算块，以生成特征向量和，其指示特征向量与GMM语音识别算法的混合分量之间的平方差的加权和。在至少一个实施例中，被建模的GMM语音识别算法包括多个高斯混合分量，并且公共计算块可操作以产生对应于多个混合分量中的每一个的特征向量分数。

7. 发明申请

US20140177955A1 SYSTEM AND METHOD FOR ADAPTIVE SKIN TONE DETECTION 有权
标题翻译：用于自适应皮肤色调检测的系统和方法
公开(公告)号：US20140177955A1
公开(公告)日：2014-06-26
申请号：US13724150
申请日：2012-12-21
申请人： Sadagopan Srinivasan , Michael E. Kounavis , Rameshkumar G. Illikkal , Ravishankar Iyer
发明人： Sadagopan Srinivasan , Michael E. Kounavis , Rameshkumar G. Illikkal , Ravishankar Iyer
IPC分类号： G06K9/46
CPC分类号： G06K9/4652 , G06K9/00375
摘要： A system and method for detecting human skin tone in one or more images. The system includes an image processing module configured to receive an image and provide contrast enhancement of the image so as to compensate for background illumination in the image. The image processing module is further configured to detect and identify regions of the contrast-enhanced image containing human skin tone based, at least in part, on the utilization of multiple color spaces and adaptively generated thresholds for each color space. A system and method consistent with the present disclosure is configure to provide accurate detection of human skin tone while accounting for variations in skin appearance due to a variety of factors, including background illumination and objects.
摘要翻译：一种用于在一个或多个图像中检测人肤色调的系统和方法。该系统包括被配置为接收图像并且提供图像的对比度增强以便补偿图像中的背景照明的图像处理模块。图像处理模块还被配置为至少部分地基于多个颜色空间的利用和针对每个颜色空间的自适应生成的阈值来检测和识别包含人肤色的对比度增强图像的区域。与本公开一致的系统和方法被配置为提供对人肤色调的准确检测，同时考虑到由于各种因素（包括背景照明和物体）引起的皮肤外观的变化。

8. 发明申请

US20140095799A1 DIFFERENTIATING CACHE RELIABILITY TO REDUCE MINIMUM ON-DIE VOLTAGE 有权
标题翻译：降低缓存电容的缓存可靠性
公开(公告)号：US20140095799A1
公开(公告)日：2014-04-03
申请号：US13631894
申请日：2012-09-29
申请人： Zhen Fang , Shih-Lien Lu , Ravishankar Iyer , Srihari Makineni
发明人： Zhen Fang , Shih-Lien Lu , Ravishankar Iyer , Srihari Makineni
IPC分类号： G06F12/12
CPC分类号： G06F11/004 , G06F1/3225 , G06F1/3275 , G06F1/3296 , G11C5/14 , G11C5/141 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions.
摘要翻译：系统和方法可以提供确定存储器访问请求是否是容错的，以及如果存储器访问请求是容错的，则将存储器访问请求路由到可靠的存储器区域。此外，如果存储器访问请求是容错的，则存储器访问请求可以被路由到不可靠的存储器区域。在一个示例中，使用不可靠的存储区域使得能够降低包含可靠和不可靠的存储器区域的管芯的最小工作电压电平。

9. 发明申请

US20130326101A1 INTERRUPT RETURN INSTRUCTION WITH EMBEDDED INTERRUPT SERVICE FUNCTIONALITY 有权
标题翻译：具有嵌入式中断服务功能的中断返回指令
公开(公告)号：US20130326101A1
公开(公告)日：2013-12-05
申请号：US13997651
申请日：2011-12-22
申请人： Zhen Fang , Xiaowei Jiang , Shihari Makineni , Ramesh G. Illikkal , Ravishankar Iyer
发明人： Zhen Fang , Xiaowei Jiang , Shihari Makineni , Ramesh G. Illikkal , Ravishankar Iyer
IPC分类号： G06F13/24
CPC分类号： G06F9/3016 , G06F9/327 , G06F9/3861 , G06F9/4806 , G06F9/4812 , G06F13/24
摘要： An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
摘要翻译：描述了在半导体芯片上实现的指令流水线。半导体芯片包括执行单元，以执行中断处理指令。存储电路用于保存不同组的微操作，其中每组微操作都要处理不同的中断。第一逻辑电路，用于执行一组所述微操作组，以处理所述集合设计的中断。第二逻辑电路，用于在所述第一逻辑电路处理所述中断时将程序流返回到调用程序。

10. 发明授权

US08392657B2 Monitoring cache usage in a distributed shared cache 有权
标题翻译：监控分布式共享缓存中的缓存使用情况
公开(公告)号：US08392657B2
公开(公告)日：2013-03-05
申请号：US12587670
申请日：2009-10-09
申请人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
发明人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864
摘要： An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，该装置包括多个组的高速缓冲存储器。高速缓冲存储器中的每个集合具有多个高速缓存行。该装置还包括至少一个进程资源表。进程资源表维护多个高速缓存行的高速缓存行占用数。具体地说，每个高速缓存行的高速缓存线占用率表示高速缓存存储由计算机系统上运行的进程使用的信息的高速缓存行数。此外，处理资源表存储比高速缓冲存储器中的高速缓存行总数少的高速缓存行的占用数。

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