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1. 发明专利

GB2602525A Constant multiplication by division 未知
公开(公告)号：GB2602525A
公开(公告)日：2022-07-06
申请号：GB202109460
申请日：2021-06-30
申请人： IMAGINATION TECH LTD
发明人： THOMAS ROSE , SAM ELLIOTT
IPC分类号： G06F7/525 , G06F7/487 , G06F7/523
摘要： A fixed logic circuit configured to determine one or more of the most significant bits of the multiplication operation α∗ x, where α is an integer constant, x is an integer variable in the range 0 to 2m − 1, and m is a positive integer, the fixed logic circuit comprising: division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation: 2ix q where i is the minimum positive value which satisfies: 2i_______ >a * (2m-1) + 1 (2imod a) q = 2i α and output logic configured to provide the one or more most significant bits of the result of the division operation as the respective one or more most significant bits of the multiplication operation α * x

2. 发明专利

GB2594109B Verification of hardware design for component that evaluates an algebraic expression using decomposition and recombination 未知
公开(公告)号：GB2594109B
公开(公告)日：2022-06-15
申请号：GB202016320
申请日：2020-10-14
申请人： IMAGINATION TECH LTD
发明人： SAM ELLIOTT , RACHEL EDMONDS
IPC分类号： G06F30/33
摘要： Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. The methods include: for each of the plurality of sub-algebraic expressions, verifying that an instantiation of the hardware design generates a correct output to that sub-algebraic expression for valid values of each variable in that sub-algebraic expression; and for each of one or more combinations of sub-algebraic expressions, formally verifying that an instantiation of the hardware design generates a correct output to that combination by comparing an output of an instantiation of the hardware design under a first set of constraints to an output of an instantiation of the hardware design under a second set of constraints; wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

3. 发明专利

GB2537939A Control path verification of hardware design for pipelined process 未知
公开(公告)号：GB2537939A
公开(公告)日：2016-11-02
申请号：GB201507571
申请日：2015-05-01
申请人： IMAGINATION TECH LTD
发明人： ASHISH DARBARI , SAM ELLIOTT
IPC分类号： G06F9/38 , G06F11/30 , G06F11/34 , G06F17/50
摘要： Methods and systems are provided for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. A method 400 comprises: monitoring 402 data input to the pipelined process to determine when watched data has been input 404 to the pipelined process; in response to determining the watched data has been input to the pipelined process, counting 406 a number of progressing clock cycles for the watched data; and evaluating 410 an assertion establishing that, when the watched data is output 408 from the pipelined process, the counted number of progressing clock cycles for the watched data is equal to one of one or more predetermined numbers of clock cycles. Determining whether a clock cycle is a progressing clock cycle for the watched data may be based on an external event control signal, such as a stall signal or an interrupt signal, where on detection of a stall signal the counter may not be incremented, and on detection of an interrupt signal the counter may be reset. Verification of the control path facilitates checking whether data moves or advances through the pipeline as expected.

4. 发明专利

GB2599929A Verification of hardware design for an integrated circuit that implements a function that is polynomial in one or more sub-functions 未知
公开(公告)号：GB2599929A
公开(公告)日：2022-04-20
申请号：GB202016314
申请日：2020-10-14
申请人： IMAGINATION TECH LTD
发明人： RACHEL EDMONDS , SAM ELLIOTT
IPC分类号： G06F30/3323 , G06F119/16
摘要： Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k + 1 when the value of the kth difference is not predetermined.

5. 发明专利

GB2588134B Verification of hardware design for data transformation component 未知
公开(公告)号：GB2588134B
公开(公告)日：2021-12-01
申请号：GB201914552
申请日：2019-10-08
申请人： IMAGINATION TECH LTD
发明人： SAM ELLIOTT
IPC分类号： G06F30/3323
摘要： Methods and systems for verifying a hardware design for a main data transformation component. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. The method includes: (a) for each of the plurality of leaf data transformation components, verifying that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions; and (b) for each of the one or more parent data transformation components, formally verifying, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that is configured to for a specific input transaction to the child data transformation component produce a specific output transaction with a causal deterministic relationship to the specific input transaction. During formal verification the formal verification tool is configured to select the specific input transaction and the specific output transaction pair to be each possible valid input transaction and valid output transaction pair for the child data transformation component.

6. 发明专利

GB2594109A Verification of hardware design for component that evaluates an algebraic expression using decomposition and recombination 未知
公开(公告)号：GB2594109A
公开(公告)日：2021-10-20
申请号：GB202016320
申请日：2020-10-14
申请人： IMAGINATION TECH LTD
发明人： SAM ELLIOTT , RACHEL EDMONDS
IPC分类号： G06F30/33
摘要： Verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main expression is representable as a lossless combination of sub-algebraic expressions 100, and a number of the variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-expressions 102. The verification includes, for each of the sub-expressions, verifying that an instantiation of the hardware design generates a correct output to that sub-expression for valid values of each variable in that sub-expression; and for each of the combinations of sub-expressions, formally verifying that an instantiation of the hardware design generates a correct output to that combination by comparing an output of an instantiation of the hardware design under a first set of constraints to an equivalent instantiation output under a second set of constraints 104; wherein the one or more combinations comprises a combination that is equivalent to the main expression.

7. 发明专利

GB2572665B Verification of hardware design for data transformation pipeline 未知
公开(公告)号：GB2572665B
公开(公告)日：2020-07-08
申请号：GB201818108
申请日：2018-11-06
申请人： IMAGINATION TECH LTD
发明人： SAM ELLIOTT
IPC分类号： G06F30/3323
摘要： Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

8. 发明专利

GB2543511B Rounding reciprocal square root results 未知
公开(公告)号：GB2543511B
公开(公告)日：2018-07-25
申请号：GB201518478
申请日：2015-10-19
申请人： IMAGINATION TECH LTD
发明人： CASPER VAN BENTHEM , SAM ELLIOTT
IPC分类号： G06F7/499 , G06F7/483 , G06F7/552
摘要： Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term. To be accompanied, when published, by FIG. 3 of the accompanying drawings.

9. 发明专利

GB2583333B Verification of hardware design for an integrated circuit that implements a function that is polynomial in one or more input variables 未知
公开(公告)号：GB2583333B
公开(公告)日：2022-03-16
申请号：GB201905297
申请日：2019-04-15
申请人： IMAGINATION TECH LTD
发明人： SAM ELLIOTT , ROBERT MCKEMEY , MAX FREIBURGHAUS
IPC分类号： G06F30/3323 , G06F30/3308
摘要： Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant k th difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

10. 发明专利

GB2593200A Method and system for verifying a sorter 未知
公开(公告)号：GB2593200A
公开(公告)日：2021-09-22
申请号：GB202003988
申请日：2020-03-19
申请人： IMAGINATION TECH LTD
发明人： SAM ELLIOTT , SIMON GAULTER , THOMAS FERRERE , FAIZAN NAZAR
IPC分类号： G06F30/3323 , G06F7/24
摘要： A method of generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

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