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1. 发明申请

US20140188470A1 FLEXIBLE ARCHITECTURE FOR ACOUSTIC SIGNAL PROCESSING ENGINE 有权
标题翻译：声学信号处理发动机的灵活结构
公开(公告)号：US20140188470A1
公开(公告)日：2014-07-03
申请号：US13732329
申请日：2012-12-31
申请人： Jenny Chang , Michael E. Deisher , Ravishankar Iyer
发明人： Jenny Chang , Michael E. Deisher , Ravishankar Iyer
IPC分类号： G10L15/28
CPC分类号： G10L15/14
摘要： A disclosed speech processor includes a front end to receive a speech input and generate a feature vector indicative of a portion of the speech input and a Gaussian mixture (GMM) circuit to receive the feature vector, model any one of a plurality of GMM speech recognition algorithms, and generate a GMM score for the feature vector based on the GMM speech recognition algorithm modeled. In at least one embodiment, the GMM circuit includes a common compute block to generate feature a vector sum indicative of a weighted sum of differences squares between the feature vector and a mixture component of the GMM speech recognition algorithm. In at least one embodiment, the GMM speech recognition algorithm being modeled includes a plurality of Gaussian mixture components and the common compute block is operable to generate feature vector scores corresponding to each of the plurality of mixture components.
摘要翻译：公开的语音处理器包括前端，用于接收语音输入并产生指示语音输入的一部分的特征向量和接收特征向量的高斯混合（GMM）电路，模拟多个GMM语音识别中的任何一个算法，并且基于建模的GMM语音识别算法为特征向量生成GMM得分。在至少一个实施例中，GMM电路包括公共计算块，以生成特征向量和，其指示特征向量与GMM语音识别算法的混合分量之间的平方差的加权和。在至少一个实施例中，被建模的GMM语音识别算法包括多个高斯混合分量，并且公共计算块可操作以产生对应于多个混合分量中的每一个的特征向量分数。

2. 发明授权

US09769050B2 End-to-end datacenter performance control 有权
公开(公告)号：US09769050B2
公开(公告)日：2017-09-19
申请号：US14581595
申请日：2014-12-23
申请人： Andrew J. Herdrich , Patrick Connor , Dinesh Kumar , Alexander W. Min , Ravishankar Iyer , Daniel J. Dahle , Kapil Sood , Jeffrey B. Shaw
发明人： Andrew J. Herdrich , Patrick Connor , Dinesh Kumar , Alexander W. Min , Ravishankar Iyer , Daniel J. Dahle , Kapil Sood , Jeffrey B. Shaw
IPC分类号： G06F15/173 , H04L12/26 , H04L12/24 , G06F12/084 , G06F12/0811
CPC分类号： H04L43/50 , G06F12/0811 , G06F12/084 , G06F2212/152 , G06F2212/601 , H04L41/0896 , H04L41/5009 , H04L41/5025 , H04L41/5035 , H04L41/5096 , H04L43/16
摘要： In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.

3. 发明授权

US09755997B2 Efficient peer-to-peer communication support in SoC fabrics 有权
公开(公告)号：US09755997B2
公开(公告)日：2017-09-05
申请号：US13810033
申请日：2012-01-13
申请人： Bin Li , Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal
发明人： Bin Li , Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal
IPC分类号： H04L12/58 , G06F13/40 , H04L12/933
CPC分类号： H04L51/04 , G06F13/4022 , G06F2213/0038 , H04L49/109 , H04L51/30
摘要： Methods and apparatus for efficient peer-to-peer communication support in interconnect fabrics. Network interfaces associated with agents are implemented to facilitate peer-to-peer transactions between agents in a manner that ensures data accesses correspond to the most recent update for each agent. This is implemented, in part, via use of non-posted “dummy writes” that are sent from an agent when the destination between write transactions originating from the agent changes. The dummy writes ensure that data corresponding to previous writes reach their destination prior to subsequent write and read transactions, thus ordering the peer-to-peer transactions without requiring the use of a centralized transaction ordering entity.

4. 发明授权

US08898390B2 Scheduling workloads based on cache asymmetry 有权
标题翻译：基于缓存不对称调度工作负载
公开(公告)号：US08898390B2
公开(公告)日：2014-11-25
申请号：US13042547
申请日：2011-03-08
申请人： Xiaowei Jiang , Li Zhao , Ravishankar Iyer
发明人： Xiaowei Jiang , Li Zhao , Ravishankar Iyer
IPC分类号： G06F13/18 , G06F12/08 , G06F9/48 , G06F9/46
CPC分类号： G06F12/0842 , G06F9/46 , G06F9/4881 , G06F2209/483
摘要： In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.
摘要翻译：在一个实施例中，处理器包括第一高速缓存和第二高速缓存，与第一高速缓存相关联的第一核和与第二高速缓存相关联的第二核。高速缓存具有非对称尺寸，并且调度器可以至少部分地基于对至少一个线程的训练阶段期间获得的不对称性和结果高速缓存性能信息的认识来智能地将线程调度到核心。

5. 发明申请

US20140240326A1 Method, Apparatus, System For Representing, Specifying And Using Deadlines 有权
标题翻译：方法，设备，代表，指定和使用期限的系统
公开(公告)号：US20140240326A1
公开(公告)日：2014-08-28
申请号：US13780117
申请日：2013-02-28
申请人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
发明人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
IPC分类号： G06F3/06
CPC分类号： G06F13/00 , G06F9/00 , G06F13/1626 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在存储器请求完成之前指示最大等待时间的最后期限值。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

6. 发明申请

US20140201471A1 Arbitrating Memory Accesses Via A Shared Memory Fabric 有权
标题翻译：仲裁存储器通过共享存储器访问
公开(公告)号：US20140201471A1
公开(公告)日：2014-07-17
申请号：US13743795
申请日：2013-01-17
申请人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Jose S. Niell , Debra Bernstein , Deepak Limaye , Ioannis T. Schoinas , Ravishankar Iyer
发明人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Jose S. Niell , Debra Bernstein , Deepak Limaye , Ioannis T. Schoinas , Ravishankar Iyer
IPC分类号： G06F13/16
CPC分类号： G06F13/1663 , G06F13/1605 , G06F13/161 , G06F2212/1024 , G06F2213/0064 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

7. 发明授权

US08781234B2 Optimized fast hessian matrix computation architecture 有权
标题翻译：优化的快捷希思矩阵计算架构
公开(公告)号：US08781234B2
公开(公告)日：2014-07-15
申请号：US12896077
申请日：2010-10-01
申请人： Yong Zhang , Ravishankar Iyer , Rameshkumar G. Illikkal , Donald K. Newell , Jianping Zhou
发明人： Yong Zhang , Ravishankar Iyer , Rameshkumar G. Illikkal , Donald K. Newell , Jianping Zhou
IPC分类号： G06K9/50 , G06K9/46 , G06K9/62 , G06K9/66
CPC分类号： G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
摘要： Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
摘要翻译：识别图像的方法和系统可以包括具有硬件模块的装置，该硬件模块具有对于图像中的多个向量的逻辑，基于图像矢量的偶数像素确定第一中间计算，并且基于奇数来确定第二中间计算图像矢量的像素。逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。

8. 发明申请

US20140189704A1 HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法
公开(公告)号：US20140189704A1
公开(公告)日：2014-07-03
申请号：US13730539
申请日：2012-12-28
申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/50
CPC分类号： G06F9/5044 , G06F9/45533 , G06F9/5077 , G06F9/5094 , G06F15/80 , Y02D10/22
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心组内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行从第一组或第二组物理处理器到第一虚拟处理器。

9. 发明授权

US08718096B2 Packet coalescing 有权
标题翻译：分组聚合
公开(公告)号：US08718096B2
公开(公告)日：2014-05-06
申请号：US12980682
申请日：2010-12-29
申请人： Srihari Makineni , Ravishankar Iyer , David Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravishankar Iyer , David Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04J3/24
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

10. 发明申请

US20140095806A1 CONFIGURABLE SNOOP FILTER ARCHITECTURE 审中-公开
标题翻译：可配置SNOOP过滤器架构
公开(公告)号：US20140095806A1
公开(公告)日：2014-04-03
申请号：US13631935
申请日：2012-09-29
申请人： Carlos A. Flores Fajardo , German Fabila Garcia , Li Zhao , Ravishankar Iyer
发明人： Carlos A. Flores Fajardo , German Fabila Garcia , Li Zhao , Ravishankar Iyer
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/601 , Y02D10/13
摘要： Configurable snoop filters. A memory system is coupled with one or more processing cores. A coherent system fabric couples the memory system with the one or more processing cores. The coherent system fabric comprising at least a configurable snoop filter that is configured based on workload. The configurable snoop filter having a configurable snoop filter directory and a bloom filter. The configurable snoop filter and the bloom filter include runtime configuration parameters that are used to selectively limit snoop traffic.
摘要翻译：可配置的窥探过滤器存储器系统与一个或多个处理核心耦合。一致的系统结构将存储器系统与一个或多个处理核心耦合。所述相干系统结构至少包括基于工作负载配置的可配置窥探过滤器。可配置的窥探过滤器具有可配置的窥探过滤器目录和绽放过滤器。可配置的窥探过滤器和布隆过滤器包括用于选择性地限制窥探流量的运行时配置参数。

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