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1. 外观设计

USD979956S1 Sofa bed 有权
公开(公告)号：USD979956S1
公开(公告)日：2023-03-07
申请号：US29811123
申请日：2021-10-12
申请人： John Chen
设计人： John Chen

2. 外观设计

USD795667S1 Hammer 有权
公开(公告)号：USD795667S1
公开(公告)日：2017-08-29
申请号：US29521097
申请日：2015-03-19
申请人： John Chen
设计人： John Chen

3. 发明授权

US09159828B2 Top drain LDMOS 有权
标题翻译：顶级漏极LDMOS
公开(公告)号：US09159828B2
公开(公告)日：2015-10-13
申请号：US13436308
申请日：2012-03-30
申请人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
发明人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/45
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1083 , H01L29/161 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/66681
摘要： In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
摘要翻译：在一个实施例中，本发明公开了一种支撑在半导体衬底上的顶排侧向扩散金属氧化物场效应半导体（TD-LDMOS）器件。 TD-LDMOS包括设置在半导体衬底的底表面上的源电极。 TD-LDMOS还包括设置在设置在半导体衬底的顶表面上的平面栅极的两个相对侧上的源极区域和漏极区域，其中源极区域包围在构成漂移区域的体区域中作为横向电流通道在平面栅极下面的源极区域和漏极区域之间。 TD-LDMOS还包括至少填充有导电材料并且从顶表面附近的主体区域向下垂直延伸的沟槽，以电接触设置在半导体衬底的底表面上的源电极。

4. 发明授权

US08847306B2 Direct contact in trench with three-mask shield gate process 有权
标题翻译：直接接触沟槽与三屏蔽屏蔽门工艺
公开(公告)号：US08847306B2
公开(公告)日：2014-09-30
申请号：US13343666
申请日：2012-01-04
申请人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
发明人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
IPC分类号： H01L29/66 , H01L21/336 , H01L29/423 , H01L29/78 , H01L29/40 , H01L29/45 , H01L29/49 , H01L29/08 , H01L21/265
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。第一导电材料形成在沟槽的底部。在第一导电材料上方形成由绝缘体隔开的第二导电材料。在沟槽上形成第一绝缘体层。在衬底中形成体层。源体形成在体层中。在沟槽和源极上形成第二绝缘体层。源极和栅极触点通过第二绝缘体层形成。源极和栅极金属形成在第二绝缘体层上。提供该摘要以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

5. 发明授权

US08779510B2 Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts 有权
标题翻译：采用自对准工艺制造的半导体功率器件和更可靠的电触点
公开(公告)号：US08779510B2
公开(公告)日：2014-07-15
申请号：US12802185
申请日：2010-06-01
申请人： Hamza Yilmaz , John Chen , Daniel Ng , Wenjun Li
发明人： Hamza Yilmaz , John Chen , Daniel Ng , Wenjun Li
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811 , H01L29/866 , H01L29/872 , H01L29/8725
摘要： This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
摘要翻译：本发明公开了一种半导体功率器件，其包括设置在半导体衬底的顶表面附近的多个顶部电端子。顶部电气端子中的每一个包括在半导体衬底的顶表面附近形成为硅化物接触层的端子接触层。半导体功率器件的沟槽栅极从半导体衬底的顶表面打开，并且每个沟槽栅极包括被配置为硅化物接触层的硅化物层，硅化物层设置在略微低于半导体衬底的顶表面围绕沟槽栅极。

6. 发明授权

US08772828B2 Trench poly ESD formation for trench MOS and SGT 有权
标题翻译：沟槽MOS和SGT的沟槽聚合物ESD形成
公开(公告)号：US08772828B2
公开(公告)日：2014-07-08
申请号：US13911871
申请日：2013-06-06
申请人： Hong Chang , John Chen
发明人： Hong Chang , John Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7393 , H01L27/0259 , H01L29/7827
摘要： A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：半导体器件包括设置在具有至少沟槽底部的多晶硅衬底的沟槽中的半导体材料。半导体材料包括不同的掺杂区域，其被配置为在沟槽中形成的PNP或NPN结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

7. 发明授权

US08618601B2 Shielded gate trench MOSFET with increased source-metal contact 有权
标题翻译：屏蔽栅极沟槽MOSFET增加了源极 - 金属接触
公开(公告)号：US08618601B2
公开(公告)日：2013-12-31
申请号：US13016804
申请日：2011-01-28
申请人： John Chen
发明人： John Chen
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L21/26513 , H01L21/26586 , H01L29/0847 , H01L29/0865 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42372 , H01L29/456 , H01L29/4933 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.
摘要翻译：一种半导体器件，形成在具有衬底顶表面的半导体衬底上，包括：从衬底顶表面延伸到半导体衬底中的栅极沟槽; 栅极沟槽中的栅电极; 设置在所述栅电极上的电介质材料; 与栅极沟槽相邻的体区; 源区域，其嵌入在所述体区中，所述源极区域的至少一部分延伸到所述介电材料之上; 接触沟槽，其允许诸如源极区域和身体区域之间的电接触的接触; 以及设置在栅极沟槽开口的至少一部分，源极区的至少一部分以及接触沟槽的至少一部分之上的金属层。

8. 发明授权

US08587061B2 Power MOSFET device with self-aligned integrated Schottky diode 有权
标题翻译：功率MOSFET器件，具有自对准集成肖特基二极管
公开(公告)号：US08587061B2
公开(公告)日：2013-11-19
申请号：US13559502
申请日：2012-07-26
申请人： Yeeheng Lee , Yongping Ding , John Chen
发明人： Yeeheng Lee , Yongping Ding , John Chen
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/782
摘要： A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.
摘要翻译：功率MOSFET器件及其制造方法包括以下步骤：在接触沟槽的底部的中间区域选择性地沉积第一导电材料，并与光掺杂的N型外延层接触以形成肖特基结，并沉积第二导电材料导电材料在接触沟槽的侧壁和底角处并与P型重掺杂体区域接触以形成欧姆结。第一和第二导电材料可以分别优化欧姆接触和肖特基接触的性能而不折不扣。同时，接触沟槽的角部被P型重掺杂区域围绕，从而有效地减少了在接触沟槽的拐角处积聚的漏电流。

9. 发明授权

US08551831B2 Silicon germanium and polysilicon gate structure for strained silicon transistors 有权
标题翻译：用于应变硅晶体管的硅锗和多晶硅栅极结构
公开(公告)号：US08551831B2
公开(公告)日：2013-10-08
申请号：US12234393
申请日：2008-09-19
申请人： Da Wei Gao , Bei Zhu , Hanming Wu , John Chen , Paolo Bonfanti
发明人： Da Wei Gao , Bei Zhu , Hanming Wu , John Chen , Paolo Bonfanti
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7848
摘要： An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others.
摘要翻译：集成电路半导体器件，例如MOS，CMOS。该器件具有半导体衬底。该器件还具有覆盖半导体衬底的电介质层和覆盖在介电层上的栅极结构。电介质层在栅极结构的边缘上形成侧壁间隔物。凹陷区域在侧壁间隔结构内的栅极结构的一部分内。外延填充材料在凹陷区域内。该器件在半导体衬底内具有源极凹陷区域和漏极凹陷区域，并且耦合到栅极结构。该器件在源极凹陷区域内和漏极凹陷区域内具有外延填充材料。源极区域和漏极区域之间的沟道区域至少从形成在源极区域和漏极区域中的填充材料的应变特性中得到。根据实施例，填充材料可以是任何合适的物质，例如硅锗，碳化硅等。

10. 发明申请

US20130221430A1 NANO-TUBE MOSFET TECHNOLOGY AND DEVICES 有权
标题翻译：纳米管MOSFET技术和器件
公开(公告)号：US20130221430A1
公开(公告)日：2013-08-29
申请号：US13594837
申请日：2012-08-26
申请人： Hamza Yilmaz , Daniel Ng , Lingpeng Guan , Anup Bhalla , Wilson Ma , Moses Ho , John Chen
发明人： Hamza Yilmaz , Daniel Ng , Lingpeng Guan , Anup Bhalla , Wilson Ma , Moses Ho , John Chen
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/404 , H01L29/66136 , H01L29/66348 , H01L29/66666 , H01L29/66734 , H01L29/7322 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/8083 , H01L29/861 , H01L29/872
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

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