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1. 发明授权

US08753942B2 Silicon and silicon germanium nanowire structures 有权
标题翻译：硅和硅锗纳米线结构
公开(公告)号：US08753942B2
公开(公告)日：2014-06-17
申请号：US12958179
申请日：2010-12-01
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/775 , H01L29/66 , H01L21/336 , H01L21/762 , H01L29/772 , B82Y40/00
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

2. 发明申请

US20120138886A1 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 有权
标题翻译：硅和硅锗纳米结构
公开(公告)号：US20120138886A1
公开(公告)日：2012-06-07
申请号：US12958179
申请日：2010-12-01
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/775 , H01L29/66 , H01L21/336 , H01L21/762 , B82Y40/00 , H01L29/772
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

3. 发明授权

US09129829B2 Silicon and silicon germanium nanowire structures 有权
标题翻译：硅和硅锗纳米线结构
公开(公告)号：US09129829B2
公开(公告)日：2015-09-08
申请号：US14274592
申请日：2014-05-09
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/165 , H01L29/06 , B82Y10/00 , H01L21/762 , H01L29/16 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

4. 发明授权

US07650525B1 SPI-4.2 dynamic implementation without additional phase locked loops 有权
标题翻译： SPI-4.2动态实现，无需附加锁相环
公开(公告)号：US07650525B1
公开(公告)日：2010-01-19
申请号：US11538157
申请日：2006-10-03
申请人： Peter Chang , Amrik Bains , Ajoy Aswadhati , Edward Wang
发明人： Peter Chang , Amrik Bains , Ajoy Aswadhati , Edward Wang
IPC分类号： G06F1/00
CPC分类号： H04L7/0337 , H04L25/0272 , H04L25/14
摘要： A method and apparatus for receiving clocked data signals such as SPI-4.2 data signals is described. In one embodiment, each data signal lane is deskewed with respect to the clock by oversampling the signal on that lane, and considering multiple versions of a data sequence at different temporal offsets to the clock for correct reception of a training sequence. One of the temporal offsets is subsequently selected to provide the received bit sequence for that lane. Other embodiments are described and claimed.
摘要翻译：描述了用于接收诸如SPI-4.2数据信号的时钟数据信号的方法和装置。在一个实施例中，通过对该通道上的信号进行过采样，并且考虑与时钟不同的时间偏移的数据序列的多个版本以正确接收训练序列，使每个数据信号通道相对于时钟进行相移校正。随后选择一个时间偏移量来提供该通道的接收位序列。描述和要求保护其他实施例。

5. 发明授权

US07515158B2 Modularly configurable memory system for LCD TV system 有权
标题翻译：用于液晶电视系统的模块化可配置存储系统
公开(公告)号：US07515158B2
公开(公告)日：2009-04-07
申请号：US11158872
申请日：2005-06-22
申请人： Peter Chang , Kuan Fu Chen
发明人： Peter Chang , Kuan Fu Chen
IPC分类号： G06T1/60
CPC分类号： H04N21/44004 , G09G5/001 , G09G5/39 , G09G2360/12 , H04N19/423 , H04N21/42692 , H04N21/443
摘要： A configurable memory system provides a high bandwidth, low latency, no wait state data path to a memory system functioning as a frame buffer for a digital video processing system. The configurable memory system has configurable channels that are programmable to control the access pattern of the memory controller. Once the configurable channels are programmed, the memory controller can generate the necessary address, timing, and control signals for selectively writing the data to and reading the data from the selected blocks of the array of memory devices continuously access the memory and move the data to the channel buffers. The channel buffer receives, retains, and transfers a defined segment of the data as defined by the segment pattern between the processing system and the array of memory devices, such that the processing system is able to transfer and receive the data continuously according to data requirements of the processing system.
摘要翻译：可配置的存储器系统提供高带宽，低等待时间，无等待状态数据路径到用作数字视频处理系统的帧缓冲器的存储器系统。可配置存储器系统具有可编程的可配置通道，以控制存储器控制器的访问模式。一旦可配置的通道被编程，存储器控制器可以产生必要的地址，定时和控制信号，用于选择性地将数据写入存储器件阵列的所选块并从其中读取数据，并持续访问存储器并将数据移动到通道缓冲区。信道缓冲器接收，保留和传送由处理系统和存储器件阵列之间的段模式定义的数据的定义段，使得处理系统能够根据数据要求连续地传送和接收数据的处理系统。

6. 发明申请

US20080166900A1 Structure of wire output 审中-公开
标题翻译：电线输出结构
公开(公告)号：US20080166900A1
公开(公告)日：2008-07-10
申请号：US11649235
申请日：2007-01-04
申请人： Peter Chang
发明人： Peter Chang
IPC分类号： H01R12/16 , H01R13/46
CPC分类号： H01R13/6658 , H01R12/718 , H01R13/6581 , H01R13/7175 , H01R13/719 , H01R25/00
摘要： A structure of wire output is mainly composed by a main board wire set and a peripheral wire set; the characteristic lies in: the peripheral wire set is composed of a set of electric conducting wires connected to input/output terminals of a circuit board, which comprises 4 to 8 sockets that are connected to electric conducting wires via printed circuits on the circuit board. Accordingly, the said structure of wire output provides the computer with enhanced connection to various peripherals and the power supply with aesthetic wire arrangement whiling attaining to reduce quantity of the electric conducting wires to a reasonable level.
摘要翻译：线输出结构主要由主板线组和外围线组成; 其特征在于：外围线组由连接到电路板的输入/输出端子的一组导线组成，其包括通过电路板上的印刷电路连接到导电线的4至8个插座。因此，所述电线输出结构为计算机提供了与各种外围设备的增强连接，并且电源具有美观的电线布置，从而将导电线的数量减少到合理的水平。

7. 发明申请

US20070133993A1 Optical communications using multiplexed single sideband transmission and heterodyne detection 有权
标题翻译：使用复用单边带传输和外差检测的光通信
公开(公告)号：US20070133993A1
公开(公告)日：2007-06-14
申请号：US11514381
申请日：2006-08-31
申请人： Ting Yee , Peter Chang , Shin-Sheng Tarng , Gregory Cutler , Slava Yazhgur , Ji Li , Laurence Newell , James Coward , Michael Rowan , Norman Swenson , Matthew Bashaw
发明人： Ting Yee , Peter Chang , Shin-Sheng Tarng , Gregory Cutler , Slava Yazhgur , Ji Li , Laurence Newell , James Coward , Michael Rowan , Norman Swenson , Matthew Bashaw
IPC分类号： H04J14/02
CPC分类号： H04B10/50 , H04B10/61 , H04B10/64
摘要： A transmitter subsystem generates an optical signal which contains multiple subbands of information. The subbands have different polarizations. For example, in one approach, two or more optical transmitters generate optical signals which have different polarizations. An optical combiner optically combines the optical signals into a composite optical signal for transmission across an optical fiber. In another approach, a single optical transmitter generates an optical signal with multiple subbands. The polarization of the subbands is varied, for example by using a birefringent crystal. In another aspect of the invention, each optical transmitter generates an optical signal containing both a lower optical sideband and an upper optical sideband (i.e., a double sideband optical signal). An optical filter selects the upper optical sideband of one optical signal and the lower optical sideband of another optical signal to produce a composite optical signal.
摘要翻译：发射机子系统产生包含多个信息子带的光信号。子带具有不同的极化。例如，在一种方法中，两个或更多个光发射机产生具有不同偏振的光信号。光学组合器将光学信号光学地组合成用于跨光纤传输的复合光信号。在另一种方法中，单个光发射机产生具有多个子带的光信号。例如通过使用双折射晶体来改变子带的极化。在本发明的另一方面，每个光发射机产生包含下光边带和上光边带（即，双边带光信号）的光信号。光滤波器选择一个光信号的上光边带和另一光信号的下光边带产生复合光信号。

8. 发明申请

US20060294324A1 Modularly configurable memory system for LCD TV system 有权
公开(公告)号：US20060294324A1
公开(公告)日：2006-12-28
申请号：US11158872
申请日：2005-06-22
申请人： Peter Chang , Kuan Chen
发明人： Peter Chang , Kuan Chen
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： H04N21/44004 , G09G5/001 , G09G5/39 , G09G2360/12 , H04N19/423 , H04N21/42692 , H04N21/443
摘要： A configurable memory system provides a high bandwidth, low latency, no wait state data path to a memory system functioning as a frame buffer for a digital video processing system. The configurable memory system has configurable channels that are programmable to control the access pattern of the memory controller. Once the configurable channels are programmed, the memory controller can generate the necessary address, timing, and control signals for selectively writing the data to and reading the data from the selected blocks of the array of memory devices continuously access the memory and move the data to the channel buffers. The channel buffer receives, retains, and transfers a defined segment of the data as defined by the segment pattern between the processing system and the array of memory devices, such that the processing system is able to transfer and receive the data continuously according to data requirements of the processing system.

9. 发明申请

US20060071299A1 Independently accessed double-gate and tri-gate transistors in same process flow 有权
标题翻译：独立访问的双栅极和三栅极晶体管在相同的工艺流程中
公开(公告)号：US20060071299A1
公开(公告)日：2006-04-06
申请号：US10955670
申请日：2004-09-29
申请人： Brian Doyle , Peter Chang
发明人： Brian Doyle , Peter Chang
IPC分类号： H01L27/082
CPC分类号： H01L29/785 , H01L21/845 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L29/66545 , H01L29/66795
摘要： An independent access, double-gate transistor and tri-gate transistor fabricated in the same process flow is described. An insulative plug is removed from above the semiconductor body of the I-gate device, but not the tri-gate device. This allows, for instance, metalization to form on three sides of the tri-gate device, and allowing independent gates for the I-gate device.
摘要翻译：描述了在相同工艺流程中制造的独立进入，双栅极晶体管和三栅极晶体管。绝缘插头从I栅极器件的半导体主体上方移除，而不是三栅极器件。这允许例如在三栅极器件的三面上形成金属化，并允许I栅极器件的独立栅极。

10. 发明申请

US20050285160A1 Methods for forming semiconductor wires and resulting devices 审中-公开
标题翻译：用于形成半导体线和所得器件的方法
公开(公告)号：US20050285160A1
公开(公告)日：2005-12-29
申请号：US10879765
申请日：2004-06-28
申请人： Peter Chang
发明人： Peter Chang
IPC分类号： H01L21/316 , H01L21/336 , H01L21/8234 , H01L29/78 , H01L29/786
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/785
摘要： Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various wire structures and devices including these wire structures (e.g., transistors). A wire structure may comprise a wire that extends between two spaced-apart anchors, with each anchor affixed to an underlying substrate and the wire spaced apart from the substrate. Other embodiments are described and claimed.
摘要翻译：公开了从硅或其它半导体材料形成导线的方法。还公开了包括这些线结构（例如，晶体管）的各种线结构和器件。导线结构可以包括在两个间隔开的锚固件之间延伸的导线，每个锚固件固定到下面的基板上，并且导线与基板间隔开。描述和要求保护其他实施例。

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