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1. 发明授权

US08753942B2 Silicon and silicon germanium nanowire structures 有权
标题翻译：硅和硅锗纳米线结构
公开(公告)号：US08753942B2
公开(公告)日：2014-06-17
申请号：US12958179
申请日：2010-12-01
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/775 , H01L29/66 , H01L21/336 , H01L21/762 , H01L29/772 , B82Y40/00
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

2. 发明申请

US20120138886A1 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 有权
标题翻译：硅和硅锗纳米结构
公开(公告)号：US20120138886A1
公开(公告)日：2012-06-07
申请号：US12958179
申请日：2010-12-01
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/775 , H01L29/66 , H01L21/336 , H01L21/762 , B82Y40/00 , H01L29/772
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

3. 发明授权

US09129829B2 Silicon and silicon germanium nanowire structures 有权
标题翻译：硅和硅锗纳米线结构
公开(公告)号：US09129829B2
公开(公告)日：2015-09-08
申请号：US14274592
申请日：2014-05-09
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/165 , H01L29/06 , B82Y10/00 , H01L21/762 , H01L29/16 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

4. 发明申请

US20120161202A1 JUNCTIONLESS ACCUMULATION-MODE DEVICES ON PROMINENT ARCHITECTURES, AND METHODS OF MAKING SAME 有权
标题翻译：无偿建筑物上的无连续累积模式设备及其制造方法
公开(公告)号：US20120161202A1
公开(公告)日：2012-06-28
申请号：US12978248
申请日：2010-12-23
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar P. Mudanai
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar P. Mudanai
IPC分类号： H01L29/772 , H01L21/28 , H01L21/336
CPC分类号： H01L29/775 , H01L29/0669 , H01L29/205 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L2029/7857
摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
摘要翻译：通过在JAM半导体主体的突出特征之下的反向偏压带将无连接累积模式（JAM）半导体器件从半导体衬底隔离。制造JAM器件的过程包括植入和外延。

5. 发明申请

US20130334572A1 JUNCTIONLESS ACCUMULATION-MODE DEVICES ON DECOUPLED PROMINENT ARCHITECTURES 有权
标题翻译：关于解散的建筑结构的无连续累积模式设备
公开(公告)号：US20130334572A1
公开(公告)日：2013-12-19
申请号：US13964696
申请日：2013-08-12
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar Mudanai
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar Mudanai
IPC分类号： H01L29/205 , H01L29/78
CPC分类号： H01L29/775 , H01L29/0669 , H01L29/205 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L2029/7857
摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
摘要翻译：通过在JAM半导体主体的突出特征之下的反向偏压带将无连接累积模式（JAM）半导体器件从半导体衬底隔离。制造JAM器件的过程包括植入和外延。

6. 发明授权

US08507948B2 Junctionless accumulation-mode devices on prominent architectures, and methods of making same 有权
标题翻译：突出架构上的无结点累加模式设备及其制作方法
公开(公告)号：US08507948B2
公开(公告)日：2013-08-13
申请号：US12978248
申请日：2010-12-23
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar P. Mudanai
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar P. Mudanai
IPC分类号： H01L29/66
CPC分类号： H01L29/775 , H01L29/0669 , H01L29/205 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L2029/7857
摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
摘要翻译：无连接累积模式（JAM）半导体器件通过JAM半导体的突出特征之下的反向偏压带从半导体衬底隔离。制造JAM器件的过程包括植入和外延。

7. 发明申请

US20090152589A1 Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors 审中-公开
标题翻译：在三栅晶体管中提高单轴压缩应力的系统和方法
公开(公告)号：US20090152589A1
公开(公告)日：2009-06-18
申请号：US11958275
申请日：2007-12-17
申请人： Titash Rakshit , Martin D. Giles , Tahir Ghani , Anand Murthy , Stephen M. Cea
发明人： Titash Rakshit , Martin D. Giles , Tahir Ghani , Anand Murthy , Stephen M. Cea
IPC分类号： H01L29/778 , H01L21/8234
CPC分类号： H01L21/26506 , H01L21/823437 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.
摘要翻译：增加三栅极晶体管的沟道区上的单轴压应力的晶体管结构包括形成在衬底上的至少两个半导体本体，每个半导体本体具有一对横向相对的侧壁和顶表面，共同源极区形成在所述半导体主体的一端，其中所述公共源极区域耦合到所述至少两个半导体主体中的所有半导体主体，形成在所述半导体主体的另一端上的公共漏极区域，其中，所述公共漏极区域至少与所述半导体主体两个半导体主体和形成在所述至少两个半导体主体上的公共栅电极，其中所述公共栅电极为所述至少两个半导体主体中的每一个提供栅电极，并且其中所述公共栅极具有一对横向相对的侧壁，基本上垂直于半导体主体的侧壁。

8. 发明授权

US08120073B2 Trigate transistor having extended metal gate electrode 有权
标题翻译：用具有扩展金属栅电极的晶体管
公开(公告)号：US08120073B2
公开(公告)日：2012-02-21
申请号：US12317966
申请日：2008-12-31
申请人： Titash Rakshit , Stephen M. Cea , Jack T Kavalieros , Ravi Pillarisetty
发明人： Titash Rakshit , Stephen M. Cea , Jack T Kavalieros , Ravi Pillarisetty
IPC分类号： H01L29/06 , H01L29/08
CPC分类号： H01L29/785 , H01L29/66795
摘要： A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.
摘要翻译：具有延伸的金属栅电极的触发装置包括半导体本体，其具有形成在基板上的顶表面和相对的侧壁，形成在基板上并围绕半导体主体的隔离层，其中半导体主体的一部分保持暴露在隔离物的上方层，以及形成在半导体主体的顶表面和相对侧壁上的栅极堆叠，其中栅极堆叠将深度延伸到隔离层中，从而使栅极堆叠的底表面在隔离层的顶表面下方。

9. 发明授权

US08017933B2 Compositionally-graded quantum-well channels for semiconductor devices 有权
标题翻译：用于半导体器件的组成级分量子阱通道
公开(公告)号：US08017933B2
公开(公告)日：2011-09-13
申请号：US12164982
申请日：2008-06-30
申请人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Willy Rachmady , Titash Rakshit
发明人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Willy Rachmady , Titash Rakshit
IPC分类号： H01L31/072
CPC分类号： H01L29/7784 , H01L29/201 , H01L29/4236 , H01L29/66462
摘要： A compositionally-graded quantum well channel for a semiconductor device is described. A semiconductor device includes a semiconductor hetero-structure disposed above a substrate and having a compositionally-graded quantum-well channel region. A gate electrode is disposed in the semiconductor hetero-structure, above the compositionally-graded quantum-well channel region. A pair of source and drain regions is disposed on either side of the gate electrode.
摘要翻译：描述了用于半导体器件的组成级分量子阱沟道。半导体器件包括设置在衬底之上并具有组成级分的量子阱沟道区的半导体异质结构。在半导体异质结构中，栅极电极设置在成分梯度的量子阱沟道区之上。一对源区和漏区设置在栅电极的两侧。

10. 发明申请

US20090321717A1 COMPOSITIONALLY-GRADED QUANTUM-WELL CHANNELS FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的组合式量子阱通道
公开(公告)号：US20090321717A1
公开(公告)日：2009-12-31
申请号：US12164982
申请日：2008-06-30
申请人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Willy Rachmady , Titash Rakshit
发明人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Willy Rachmady , Titash Rakshit
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/7784 , H01L29/201 , H01L29/4236 , H01L29/66462
摘要： A compositionally-graded quantum well channel for a semiconductor device is described. A semiconductor device includes a semiconductor hetero-structure disposed above a substrate and having a compositionally-graded quantum-well channel region. A gate electrode is disposed in the semiconductor hetero-structure, above the compositionally-graded quantum-well channel region. A pair of source and drain regions is disposed on either side of the gate electrode.
摘要翻译：描述了用于半导体器件的组成级分量子阱沟道。半导体器件包括设置在衬底之上并具有组成级分的量子阱沟道区的半导体异质结构。在半导体异质结构中，栅极电极设置在成分梯度的量子阱沟道区之上。一对源区和漏区设置在栅电极的两侧。

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