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1. 发明申请

US20060189048A1 Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer 有权
标题翻译：使用封端的多晶硅层减少PMOS器件的掺杂剂扩散的方法来应变NMOS器件
公开(公告)号：US20060189048A1
公开(公告)日：2006-08-24
申请号：US11060841
申请日：2005-02-18
申请人： Manoj Mehrotra , Lahir Adam , Song Zhao , Mahalingam Nandakumar
发明人： Manoj Mehrotra , Lahir Adam , Song Zhao , Mahalingam Nandakumar
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/6659 , H01L29/7843 , Y10S438/902
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.
摘要翻译：本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。源极/漏极区形成在PMOS区（102）的有源区中。执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。然后，在器件（108）上形成封端的多晶硅层。执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

2. 发明授权

US07211481B2 Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer 有权
标题翻译：使用封端的多晶硅层减少PMOS器件的掺杂剂扩散的方法来应变NMOS器件
公开(公告)号：US07211481B2
公开(公告)日：2007-05-01
申请号：US11060841
申请日：2005-02-18
申请人： Manoj Mehrotra , Lahir Shaik Adam , Song Zhao , Mahalingam Nandakumar
发明人： Manoj Mehrotra , Lahir Shaik Adam , Song Zhao , Mahalingam Nandakumar
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/6659 , H01L29/7843 , Y10S438/902
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.
摘要翻译：本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。源极/漏极区形成在PMOS区（102）的有源区中。执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。然后，在器件（108）上方形成封盖的多晶硅层。执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

3. 发明授权

US06258644B1 Mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps 有权
标题翻译：混合电压CMOS工艺，用于高可靠性和高性能的核心和I / O晶体管，减少了掩模步骤
公开(公告)号：US06258644B1
公开(公告)日：2001-07-10
申请号：US09499719
申请日：2000-02-08
申请人： Mark S. Rodder , Manoj Mehrotra , Mahalingam Nandakumar
发明人： Mark S. Rodder , Manoj Mehrotra , Mahalingam Nandakumar
IPC分类号： H01L218238
CPC分类号： H01L21/823814
摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.
摘要翻译：用于高可靠性和高性能核心晶体管和输入输出晶体管的混合电压CMOS工艺，减少了掩模步骤。在硅衬底（10）上形成栅叠层（30）。对第一种和第二种进行离子注入，以在输入输出晶体管中产生掺杂分布（70,80,90,100）。

4. 发明申请

US20080308904A1 P-DOPED REGION WITH IMPROVED ABRUPTNESS 审中-公开
标题翻译：具有改善性破坏的P区域
公开(公告)号：US20080308904A1
公开(公告)日：2008-12-18
申请号：US11763497
申请日：2007-06-15
申请人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
发明人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
IPC分类号： H01L21/425 , H01L29/36
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/268 , H01L21/324 , H01L21/823814 , H01L29/165 , H01L29/66068 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region.
摘要翻译：一种制造半导体器件的方法。该方法包括在半导体衬底中提供C原子。该方法还包括将In原子和p型掺杂剂注入被配置为具有碳原子的衬底的预定区域中。该方法还包括对半导体衬底进行热退火以将预定区域转变为激活的掺杂区域。

5. 发明申请

US20090127620A1 SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE 有权
标题翻译：具有降低栅极边缘二极管漏电的半导体器件
公开(公告)号：US20090127620A1
公开(公告)日：2009-05-21
申请号：US11941129
申请日：2007-11-16
申请人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
发明人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
IPC分类号： H01L23/00 , H01L21/425
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/165 , H01L29/6659 , H01L29/7833
摘要： Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.
摘要翻译：公开了半导体掺杂技术以及相关方法和结构，其产生具有更紧密控制的源极和漏极延伸区掺杂物分布而不显着引起栅极边缘二极管泄漏的元件。该技术遵循发现，可以用作掺杂剂如硼的扩散抑制剂的碳可能在源极和漏极延伸区域中以大量存在而产生栅极边缘二极管泄漏。作为在源极和漏极延伸区域中放置碳的替代方案，可以将碳放置在源极和漏极区域中，并且可以依靠用于激活掺杂剂的热退火将碳的少量浓度扩散到源中，漏极延伸区域，从而抑制这些区域中的掺杂剂扩散，而不会显着引起栅极边缘二极管泄漏。源极和漏极区域中增加的碳浓度可能允许源极/漏极区域的较重掺杂，导致改善的栅极电容。

6. 发明授权

US07897496B2 Semiconductor doping with reduced gate edge diode leakage 有权
标题翻译：半导体掺杂减少了栅极边缘二极管泄漏
公开(公告)号：US07897496B2
公开(公告)日：2011-03-01
申请号：US11941129
申请日：2007-11-16
申请人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
发明人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/165 , H01L29/6659 , H01L29/7833
摘要： Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.
摘要翻译：公开了半导体掺杂技术以及相关方法和结构，其产生具有更紧密控制的源极和漏极延伸区掺杂物分布而不显着引起栅极边缘二极管泄漏的元件。该技术遵循发现，可以用作掺杂剂如硼的扩散抑制剂的碳可能在源极和漏极延伸区域中以大量存在而产生栅极边缘二极管泄漏。作为在源极和漏极延伸区域中放置碳的替代方案，可以将碳放置在源极和漏极区域中，并且可以依靠用于激活掺杂剂的热退火将碳的少量浓度扩散到源中，漏极延伸区域，从而抑制这些区域中的掺杂剂扩散，而不会显着引起栅极边缘二极管泄漏。源极和漏极区域中增加的碳浓度可能允许源极/漏极区域的较重掺杂，导致改善的栅极电容。

7. 发明授权

US07615458B2 Activation of CMOS source/drain extensions by ultra-high temperature anneals 有权
标题翻译：通过超高温退火激活CMOS源极/漏极延伸
公开(公告)号：US07615458B2
公开(公告)日：2009-11-10
申请号：US11764980
申请日：2007-06-19
申请人： Amitabh Jain , Manoj Mehrotra
发明人： Amitabh Jain , Manoj Mehrotra
IPC分类号： H01L21/331
CPC分类号： H01L21/2652 , H01L21/2255 , H01L21/268 , H01L21/2686 , H01L21/823814 , H01L29/6659
摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。在栅极电介质层上形成栅电极。将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

8. 发明申请

US20090179280A1 HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDUCE DAMAGE 有权
标题翻译：具有As，P和C的高阈值NMOS源 - 漏极形成以减少损害
公开(公告)号：US20090179280A1
公开(公告)日：2009-07-16
申请号：US11972417
申请日：2008-01-10
申请人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
发明人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26586 , H01L21/823418 , H01L29/0847 , H01L29/6659 , H01L29/7833
摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed
摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。碳植入通常用于减少NLDD中的磷扩散，但有助于门极二极管泄漏（GDL）。在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。还公开了在NSD中具有小于1.1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管

9. 发明申请

US20090065880A1 Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region 有权
标题翻译：使用激光退火制造的半导体器件将应力引入通道区域
公开(公告)号：US20090065880A1
公开(公告)日：2009-03-12
申请号：US11853328
申请日：2007-09-11
申请人： Amitabh Jain , Manoj Mehrotra
发明人： Amitabh Jain , Manoj Mehrotra
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/268 , H01L21/28044 , H01L29/6656 , H01L29/7843 , H01L29/7845
摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.
摘要翻译：在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热在进行激光退火之后退火。

10. 发明申请

US20080277730A1 Semiconductor Device Manufactured Using a Laminated Stress Layer 有权
标题翻译：使用层压应力层制造的半导体器件
公开(公告)号：US20080277730A1
公开(公告)日：2008-11-13
申请号：US11745044
申请日：2007-05-07
申请人： Manoj Mehrotra , Antonio L.P Rotondaro , Puneet Kohli
发明人： Manoj Mehrotra , Antonio L.P Rotondaro , Puneet Kohli
IPC分类号： H01L21/44 , H01L29/76
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76828 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.
摘要翻译：提出了形成半导体器件的方法。该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底上形成层压应力层。层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。

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