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    • 4. 发明授权
    • Processor having multiple datapath instances
    • 具有多个数据路径实例的处理器
    • US6044448A
    • 2000-03-28
    • US991392
    • 1997-12-16
    • Nitin AgrawalSunil Nanda
    • Nitin AgrawalSunil Nanda
    • G06F7/00G06F9/30G06F9/315G06F9/38G06F15/16G06F15/78G06F15/80G06F15/00
    • G06F9/30032G06F15/7867G06F15/8015G06F9/30036G06F9/30101G06F9/30109G06F9/3885
    • A processor having a sliceable architecture wherein a slice is the minimum configuration of the processor datapath. The processor can instantiate multiple slices and each slice has a separate datapath. The total processor datapath is the sum of the number of slices multiplied by the width of a slice. Accordingly, all general purpose registers in the processor are as wide as the total datapath. A program executing on the processor can determine the maximum number of slices available in a particular processor by reading a register. In addition, a program can select the number of slices it will use by writing to a different register. The processor replicates control signals for each active slice in the processor and supports instructions for transferring data among the slices. Furthermore, the processor supports a set of instructions for fetching and storing data between multiple slices and the memory. The effective addresses of the fetch and store instructions can either be aligned or misaligned with respect to slice boundaries and doubleword boundaries in the memory.
    • 具有可切片架构的处理器,其中切片是处理器数据路径的最小配置。 处理器可以实例化多个片段,每个片段具有单独的数据路径。 总处理器数据路径是切片数乘以切片宽度的总和。 因此,处理器中的所有通用寄存器与总数据路径一样宽。 在处理器上执行的程序可以通过读取寄存器来确定特定处理器中可用的最大片数。 此外,程序可以通过写入不同的寄存器来选择要使用的片数。 处理器为处理器中的每个活动切片重复控制信号,并且支持在切片之间传送数据的指令。 此外,处理器支持用于在多个片和存储器之间取出和存储数据的一组指令。 获取和存储指令的有效地址可以相对于存储器中的切片边界和双字边界对准或不对准。
    • 9. 发明授权
    • Computer processor with two addressable memories and two stream
registers and method of data streaming of ALU operation
    • 具有两个可寻址存储器和两个流寄存器的计算机处理器和ALU操作的数据流传输方法
    • US5958038A
    • 1999-09-28
    • US966904
    • 1997-11-07
    • Nitin AgrawalSunil Nanda
    • Nitin AgrawalSunil Nanda
    • G06F7/00G06F9/30G06F9/302G06F9/345G06F9/38G06F15/00
    • G06F9/3001G06F9/3013G06F9/345G06F9/3885
    • A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation. The bits in the fields for specifying a stream register and addressing mode are positionally overlapped with the bits for specifying a particular general purpose register. This encoding allows a simple instruction decoding mechanism while enabling parallel memory accesses and address update in a compact instruction.
    • 具有经修改的哈佛架构的处理器具有第一和第二存储器,被分成第一和第二组寄存器的地址寄存器文件,第一和第二流寄存器以及用于执行数据流的通用寄存器文件。 第一和第二组寄存器分别对第一和第二存储器进行寻址,其又将数据加载到第一和第二流寄存器中。 算术逻辑单元(ALU)接受流寄存器和通用寄存器作为输入。 流指令被编码,使得单个指令指定对所选ALU输入执行的ALU操作以及在哪里存储ALU操作的结果,将新值加载到流寄存器中,并更新地址寄存器。 流指令具有三个操作数字段,分别指定下一个ALU操作的两个操作数和存储当前ALU操作结果的位置。 用于指定流寄存器和寻址模式的字段中的位与用于指定特定通用寄存器的位位置地重叠。 该编码允许简单的指令解码机制,同时在紧凑指令中实现并行存储器访问和地址更新。