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1. 发明申请

US20080177944A1 BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBY 有权
标题翻译： BUTTERFLY匹配线结构和搜索方法实现
公开(公告)号：US20080177944A1
公开(公告)日：2008-07-24
申请号：US11675440
申请日：2007-02-15
申请人： Po-Tsang Huang , Wei Hwang , Shu-Wei Chang
发明人： Po-Tsang Huang , Wei Hwang , Shu-Wei Chang
IPC分类号： G06F12/00 , G11C15/04 , G06F13/00 , G06F13/28
CPC分类号： G11C15/04
摘要： The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.
摘要翻译：本发明公开了一种蝴蝶匹配线结构和由此实现的搜索方法，其中增加匹配线的并行性以缩短搜索时间，并且使用蝴蝶型连接来降低功耗并实现最佳能量效率。通过蝶型连接，可以在原始独立的并行匹配线之间相互传输信息。当发生错误情况时，更多的后续存储单元将不被比较，但将被关闭。从而降低功耗。此外，基于XOR的条件保持器用于减少匹配时间和功耗。此外，这种电路也用于缩短蝴蝶式连接的延迟时间。

2. 发明授权

US07525827B2 Stored don't-care based hierarchical search-line scheme 有权
标题翻译：存储不进行基于分层的搜索线方案
公开(公告)号：US07525827B2
公开(公告)日：2009-04-28
申请号：US11675386
申请日：2007-02-15
申请人： Shu-Wei Chang , Wei Hwang , Ming-Hung Chang , Po-Tsang Huang
发明人： Shu-Wei Chang , Wei Hwang , Ming-Hung Chang , Po-Tsang Huang
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a plurality of local search-lines, a global search-line, a buffer and a memory memory cell. Data are stored in the blocks in order according to the length of the prefix. Data with the longest prefix is stored at the bottommost, and its don't-care state is used as the control signal of the buffer to control whether to transfer the data on the global search-line to the local search-line or not. The local search-line then transfer the value into the memory cell. There is no complex control circuit and extra storage device needed. Moreover, because the control signal directly comes from the don't-care state, power consumption on search-lines can be effectively reduced with no increase of search delay.
摘要翻译：在所提出的不存在的分层搜索线方案中，内容寻址存储器（CAM）被分成几个块。每个块包含多个本地搜索行，全局搜索行，缓冲器和存储器存储单元。数据按照前缀的长度顺序存储在块中。具有最长前缀的数据被存储在最底部，并且其不关心状态被用作缓冲器的控制信号，以控制是否将全局搜索行上的数据传送到本地搜索行。然后本地搜索行将值传送到存储单元。没有复杂的控制电路和额外的存储设备需要。此外，由于控制信号直接来自不注意状态，因此可以有效地减少搜索线上的功耗，而不增加搜索延迟。

3. 发明授权

US07903443B2 Butterfly match-line structure and search method implemented thereby 有权
标题翻译：由此实现蝴蝶匹配线结构和搜索方法
公开(公告)号：US07903443B2
公开(公告)日：2011-03-08
申请号：US11675440
申请日：2007-02-15
申请人： Po-Tsang Huang , Wei Hwang , Shu-Wei Chang
发明人： Po-Tsang Huang , Wei Hwang , Shu-Wei Chang
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.
摘要翻译：本发明公开了一种蝴蝶匹配线结构和由此实现的搜索方法，其中增加匹配线的并行性以缩短搜索时间，并且使用蝴蝶型连接来降低功耗并实现最佳能量效率。通过蝶型连接，可以在原始独立的并行匹配线之间相互传输信息。当发生错误情况时，更多的后续存储单元将不被比较，但将被关闭。从而降低功耗。此外，基于XOR的条件保持器用于减少匹配时间和功耗。此外，这种电路也用于缩短蝴蝶式连接的延迟时间。

4. 发明申请

US20080175030A1 STORED DON'T-CARE BASED HIERARCHICAL SEARCH-LINE SCHEME 有权
标题翻译：基于不相干的分层搜索线方案
公开(公告)号：US20080175030A1
公开(公告)日：2008-07-24
申请号：US11675386
申请日：2007-02-15
申请人： Shu-Wei CHANG , Wei Hwang , Ming-Hung Chang , Po-Tsang Huang
发明人： Shu-Wei CHANG , Wei Hwang , Ming-Hung Chang , Po-Tsang Huang
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a plurality of local search-lines, a global search-line, a buffer and a memory cell. Data are stored in the blocks in order according to the length of the prefix. Data with the longest prefix is stored at the bottommost, and its don't-care state is used as the control signal of the buffer to control whether to transfer the data on the global search-line to the local search-line or not. The local search-line then transfer the value into the memory cell. There is no complex control circuit and extra storage device needed. Moreover, because the control signal directly comes from the don't-care state, power consumption on search-lines can be effectively reduced with no increase of search delay.
摘要翻译：在所提出的不存在的分层搜索线方案中，内容寻址存储器（CAM）被分成几个块。每个块包含多个本地搜索行，全局搜索行，缓冲区和存储单元。数据按照前缀的长度顺序存储在块中。具有最长前缀的数据被存储在最底部，并且其不关心状态被用作缓冲器的控制信号，以控制是否将全局搜索行上的数据传送到本地搜索行。然后本地搜索行将值传送到存储单元。没有复杂的控制电路和额外的存储设备需要。此外，由于控制信号直接来自不注意状态，因此可以有效地减少搜索线上的功耗，而不增加搜索延迟。

5. 发明申请

US20130031327A1 SYSTEM AND METHOD FOR ALLOCATING CACHE MEMORY 审中-公开
标题翻译：用于分配高速缓存存储器的系统和方法
公开(公告)号：US20130031327A1
公开(公告)日：2013-01-31
申请号：US13192856
申请日：2011-07-28
申请人： Yung CHANG , Po-Tsang Huang , Wei Hwang
发明人： Yung CHANG , Po-Tsang Huang , Wei Hwang
IPC分类号： G06F12/02
CPC分类号： G06F12/0811 , G06F12/084 , Y02D10/13
摘要： Different processor elements in multi-task/multi-core system on chip may have different memory requirements at runtime. The method for adaptively allocating cache memory re-allocates the cache resource by updating the bank assignment table. According to the associativity-based partitioning scheme, centralized memory is separated into several groups of SRAM banks which are numbered differently. These groups are assigned to different processor elements to be L2 caches. The bank assignment information is recoded in bank assignment table, and is updated by system profiling engine. By changing the information in bank assignment table, the cache resource re-allocation for processor elements is achieved.
摘要翻译：多任务/多核系统芯片中的不同处理器元件在运行时可能具有不同的内存要求。用于自适应地分配高速缓存的方法通过更新银行分配表来重新分配高速缓存资源。根据基于关联性的分区方案，将集中式存储器分成若干组，这些SRAM组的编号不同。这些组被分配到不同的处理器元素以作为L2高速缓存。银行分配信息在银行分配表中重新编码，并由系统概要分析引擎更新。通过改变银行分配表中的信息，实现处理器元件的缓存资源重新分配。

6. 发明授权

US08072818B2 Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus 有权
标题翻译：双阈值电压双端口子阈值SRAM单元设备
公开(公告)号：US08072818B2
公开(公告)日：2011-12-06
申请号：US12654730
申请日：2009-12-30
申请人： Mu-Tien Chang , Po-Tsang Huang , Wei Hwang
发明人： Mu-Tien Chang , Po-Tsang Huang , Wei Hwang
IPC分类号： G11C7/00 , G11C8/16
CPC分类号： G11C8/16 , G11C11/412
摘要： The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.
摘要翻译：本发明涉及双阈值电压双端口子阈值SRAM单元装置。上述装置包括第一反相器，第二反相器，存取晶体管和读缓冲器。第一反相器和第二反相器包括用于存储数据的多个第一操作元件和多个第二操作元件。存取晶体管耦合到第一反相器和第二反相器，其中第一操作元件和第二操作元件是高阈值电压操作元件，并且存取晶体管是低阈值电压操作晶体管。读缓冲器用于执行读操作。

7. 发明授权

US07738275B2 Leakage current cut-off device for ternary content addressable memory 有权
标题翻译：用于三元内容可寻址存储器的泄漏电流截止装置
公开(公告)号：US07738275B2
公开(公告)日：2010-06-15
申请号：US12007826
申请日：2008-01-16
申请人： Po-Tsang Huang , Wen-Yen Liu , Wei Hwang
发明人： Po-Tsang Huang , Wen-Yen Liu , Wei Hwang
IPC分类号： G11C7/00
CPC分类号： G11C15/04
摘要： A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode.
摘要翻译：提供一种用于三元内容可寻址存储器的漏电流截止装置。三元内容可寻址存储器的存储单元可以处于活动模式，数据保持模式和截止模式。本发明将多模式数据保持电源门控装置应用于三元内容可寻址存储器的存储单元，以减少在数据保持模式和截止模式下通过存储单元的泄漏电流，并且支持全速操作处于活动模式。

8. 发明授权

US08427224B2 On-chip active decoupling capacitors for regulating voltage of an integrated circuit 有权
标题翻译：用于调节集成电路电压的片上有源去耦电容器
公开(公告)号：US08427224B2
公开(公告)日：2013-04-23
申请号：US13190619
申请日：2011-07-26
申请人： Tien-Hung Lin , Po-Tsang Huang , Wei Hwang
发明人： Tien-Hung Lin , Po-Tsang Huang , Wei Hwang
IPC分类号： G06F7/64
CPC分类号： H01L23/5223 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.
摘要翻译：用于调节集成电路电压的片上有源去耦电容器包括参考电压发生器，基于锁存器的比较器和开关DECAP。基于锁存的比较器用于比较由参考电压发生器产生的参考电压和集成电路的电源电压并输出比较结果。开关DECAP包括至少两个电容器和多个开关，并且基于由基于锁存器的比较器输出的比较结果，将至少两个电容器耦合到并联配置以吸收电流或串联配置以源电流。上述片上有源去耦电容器的功耗较低，但检测范围较大。

9. 发明申请

US20090161399A1 Super leakage current cut-off device for ternary content addressable memory 有权
公开(公告)号：US20090161399A1
公开(公告)日：2009-06-25
申请号：US12007824
申请日：2008-01-16
申请人： Po-Tsang Huang , Wen-Yen Liu , Wei Hwang
发明人： Po-Tsang Huang , Wen-Yen Liu , Wei Hwang
IPC分类号： G11C15/00 , G11C5/14
CPC分类号： G11C15/04
摘要： A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells.

10. 发明申请

US20100172194A1 Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus 有权
标题翻译：双阈值电压双端口子阈值SRAM单元设备
公开(公告)号：US20100172194A1
公开(公告)日：2010-07-08
申请号：US12654730
申请日：2009-12-30
申请人： Mu-Tien Chang , Po-Tsang Huang , Wei Hwang
发明人： Mu-Tien Chang , Po-Tsang Huang , Wei Hwang
IPC分类号： G11C7/00 , G11C8/16
CPC分类号： G11C8/16 , G11C11/412
摘要： The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.
摘要翻译：本发明涉及双阈值电压双端口子阈值SRAM单元装置。上述装置包括第一反相器，第二反相器，存取晶体管和读缓冲器。第一反相器和第二反相器包括用于存储数据的多个第一操作元件和多个第二操作元件。存取晶体管耦合到第一反相器和第二反相器，其中第一操作元件和第二操作元件是高阈值电压操作元件，并且存取晶体管是低阈值电压操作晶体管。读缓冲器用于执行读操作。

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