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1. 发明授权

US08928047B2 MOSFET with source side only stress 有权
标题翻译： MOSFET源极只有应力
公开(公告)号：US08928047B2
公开(公告)日：2015-01-06
申请号：US13288170
申请日：2011-11-03
申请人： Samuel Zafar Nawaz , Shaofeng Yu , Jeffrey E. Brighton , Song Zhao
发明人： Samuel Zafar Nawaz , Shaofeng Yu , Jeffrey E. Brighton , Song Zhao
IPC分类号： H01L29/772 , H01L21/336 , H01L21/20 , H01L29/78 , H01L29/165 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.
摘要翻译：集成电路仅包含源极侧的应力增强区域的晶体管。在DeMOS晶体管中，仅在源极上形成应力增强区域并且在漏极延伸中不形成应力增强区域增加了漏极延伸区域的电阻，从而能够形成减小面积的DeMOS晶体管。在MOS晶体管中，通过在源极侧形成应力增强区域，消除来自漏极侧的应力增强区域，降低晶体管泄漏，提高CHC可靠性。

2. 发明申请

US20120146054A1 MOSFET WITH SOURCE SIDE ONLY STRESS 有权
标题翻译： MOSFET，源极只有应力
公开(公告)号：US20120146054A1
公开(公告)日：2012-06-14
申请号：US13288170
申请日：2011-11-03
申请人： Samuel Zafar Nawaz , Shaofeng Yu , Jeffrey E. Brighton , Song Zhao
发明人： Samuel Zafar Nawaz , Shaofeng Yu , Jeffrey E. Brighton , Song Zhao
IPC分类号： H01L29/772 , H01L21/336 , H01L21/20
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.
摘要翻译：集成电路仅包含源极侧的应力增强区域的晶体管。在DeMOS晶体管中，仅在源极上形成应力增强区域并且在漏极延伸中不形成应力增强区域增加了漏极延伸区域的电阻，从而能够形成减小面积的DeMOS晶体管。在MOS晶体管中，通过在源极侧形成应力增强区域，消除来自漏极侧的应力增强区域，降低了晶体管泄漏，提高了CHC可靠性。

3. 发明授权

US08603875B2 CMOS process to improve SRAM yield 有权
公开(公告)号：US08603875B2
公开(公告)日：2013-12-10
申请号：US13284519
申请日：2011-10-28
申请人： Shaofeng Yu , Russell Carlton McMullan , Wah Kit Loh
发明人： Shaofeng Yu , Russell Carlton McMullan , Wah Kit Loh
IPC分类号： H01L21/8238
CPC分类号： H01L27/1104 , H01L21/823814 , H01L21/823864 , H01L21/823871 , H01L27/0922 , H01L29/0847
摘要： An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

4. 发明申请

US20110186912A1 TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER 有权
标题翻译：具有导体材料层的晶体管栅极电极
公开(公告)号：US20110186912A1
公开(公告)日：2011-08-04
申请号：US13082305
申请日：2011-04-07
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L29/772 , H01L27/092
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

5. 发明申请

US20110018031A1 TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER 有权
公开(公告)号：US20110018031A1
公开(公告)日：2011-01-27
申请号：US12893983
申请日：2010-09-29
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

6. 发明申请

US20100176462A1 METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE 审中-公开
标题翻译：同时硅化多晶硅栅极和半导体器件的源极/漏极的方法及相关器件
公开(公告)号：US20100176462A1
公开(公告)日：2010-07-15
申请号：US12731932
申请日：2010-03-25
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

7. 发明授权

US07727842B2 Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device 有权
标题翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法及相关器件
公开(公告)号：US07727842B2
公开(公告)日：2010-06-01
申请号：US11741519
申请日：2007-04-27
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L21/8234
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

8. 发明授权

US07692258B2 Photosensitive device 失效
标题翻译：感光装置
公开(公告)号：US07692258B2
公开(公告)日：2010-04-06
申请号：US11497458
申请日：2006-07-31
申请人： Miriam R. Reshotko , Shaofeng Yu , Bruce A. Block
发明人： Miriam R. Reshotko , Shaofeng Yu , Bruce A. Block
IPC分类号： H01L29/72
CPC分类号： H01L31/03529 , H01L31/0224 , H01L31/1085 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A photosensitive device for enabling high speed detection of electromagnetic radiation. The device includes recessed electrodes for providing a generally homogeneous electric field in an active region. Carriers generated in the active region are detected using the recessed electrodes.
摘要翻译：一种用于实现电磁辐射高速检测的光敏装置。该装置包括用于在有源区域中提供大致均匀的电场的凹陷电极。使用凹陷电极检测在有源区域中产生的载体。

9. 发明申请

US20100032727A1 BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HOT) DIRECT SILICON BONDED (DSB) SUBSTRATES 有权
标题翻译：混合定向技术（热）直接硅粘结（DSB）基板的边界区域缺陷减少
公开(公告)号：US20100032727A1
公开(公告)日：2010-02-11
申请号：US12538048
申请日：2009-08-07
申请人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
发明人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
IPC分类号： H01L27/092 , H01L21/20 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/187 , H01L21/324 , H01L21/76264 , H01L21/823807 , H01L21/823892 , H01L29/045 , H01L29/665
摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.
摘要翻译：用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。（100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。还公开了用本发明方法形成的集成电路。

10. 发明申请

US20080315328A1 DUAL POLY DEPOSITION AND THROUGH GATE OXIDE IMPLANTS 审中-公开
标题翻译：双重沉积物和通过浇注氧化物的植入物
公开(公告)号：US20080315328A1
公开(公告)日：2008-12-25
申请号：US12204072
申请日：2008-09-04
申请人： Shaofeng Yu , Shyh-Horng Yang
发明人： Shaofeng Yu , Shyh-Horng Yang
IPC分类号： H01L29/78
CPC分类号： H01L21/823892 , H01L21/823842 , H01L21/823857
摘要： Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.
摘要翻译：掺杂剂通过栅极电极材料和栅极电介质层的薄层以相对高的能量注入到半导体衬底的未屏蔽的第一区域中。然后将较低能量的掺杂剂注入到栅极电极材料的薄层中。然后掩蔽第一区域，并且该过程在半导体衬底的先前掩蔽的但现在未掩模的第二区域中重复。然后在栅电极材料的薄层上形成第二（通常较厚）的栅电极材料层。将厚栅极电极材料层，薄栅电极材料层和栅极电介质材料层图案化以在衬底的掺杂区域上形成一个或多个栅极结构。源极和漏极区域形成在与栅极结构相邻的衬底区域中以建立一个或多个MOS晶体管。

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