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1. 发明授权

US11080045B2 Addition instructions with independent carry chains 有权
公开(公告)号：US11080045B2
公开(公告)日：2021-08-03
申请号：US13993483
申请日：2011-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
IPC分类号： G06F9/30 , G06F9/38
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

2. 发明申请

US20140013086A1 ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS 审中-公开
标题翻译：附加说明与独立的携带链
公开(公告)号：US20140013086A1
公开(公告)日：2014-01-09
申请号：US13993483
申请日：2011-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30094 , G06F9/3838
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.
摘要翻译：提供了彼此之间没有数据依赖性的多个附加指令。第一加法指令将其进位输出存储在标志寄存器的第一标志中，而不修改标志寄存器中的第二标志。第二加法指令将其进位输出存储在标志寄存器的第二标志中，而不修改标志寄存器中的第一个标志。

3. 发明申请

US20140189306A1 ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION 有权
标题翻译：增强环路检测器驱动逻辑优化
公开(公告)号：US20140189306A1
公开(公告)日：2014-07-03
申请号：US13728273
申请日：2012-12-27
申请人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
发明人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/3885
摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.
摘要翻译：在处理器中提供增强的循环流检测机制以降低功耗。处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

4. 发明授权

US09442729B2 Minimizing bandwidth to track return targets by an instruction tracing system 有权
标题翻译：最小化带宽以通过指令跟踪系统跟踪返回目标
公开(公告)号：US09442729B2
公开(公告)日：2016-09-13
申请号：US13890654
申请日：2013-05-09
申请人： Beeman C. Strong , Matthew C. Merten , Tong Li
发明人： Beeman C. Strong , Matthew C. Merten , Tong Li
IPC分类号： G06F9/30 , H04L29/06 , G06F9/38 , G06F11/36 , G06F11/34
CPC分类号： G06F9/30145 , G06F9/3806 , G06F9/3857 , G06F11/3476 , G06F11/3636
摘要： A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the disclosure an instruction fetch unit comprising a return stack buffer (RSB) to predict a target address of a return (RET) instruction corresponding to a call (CALL) instruction. The processing device further includes a retirement unit comprising an instruction tracing module to initiate instruction tracing for instructions executed by the processing device, determine whether the target address of the RET instruction was mispredicted, determine a value of call depth counter (CDC) maintained by the instruction tracing module, and when the target address of the RET instruction was not mispredicted and when the value of the CDC is greater than zero, generate an indication that the RET instruction branches to a next linear instruction after the corresponding CALL instruction.
摘要翻译：公开了一种通过指令跟踪系统实现最小化带宽以跟踪返回目标的处理设备。本公开的处理装置包括一个指令提取单元，该单元包括用于预测与一个调用（CALL）指令相对应的返回（RET）指令的目标地址的返回栈缓冲器（RSB）。所述处理装置还包括退出单元，所述退出单元包括指令跟踪模块，用于启动由所述处理设备执行的指令的指令跟踪，确定所述RET指令的目标地址是否被错误预测，确定由所述处理设备维护的所述呼叫深度计数器指令跟踪模块，并且当RET指令的目标地址未被错误预测时，并且当CDC的值大于零时，生成指令在相应的CALL指令之后分支到下一个线性指令。

5. 发明授权

US09292288B2 Systems and methods for flag tracking in move elimination operations 有权
标题翻译：移动消除操作中标志跟踪的系统和方法
公开(公告)号：US09292288B2
公开(公告)日：2016-03-22
申请号：US13861009
申请日：2013-04-11
申请人： Vijaykumar B. Kadgi , Jeremy R. Anderson , James D. Hadley , Tong Li , Matthew C. Merten
发明人： Vijaykumar B. Kadgi , Jeremy R. Anderson , James D. Hadley , Tong Li , Matthew C. Merten
IPC分类号： G06F9/30 , G06F9/45 , G06F9/38
CPC分类号： G06F9/30105 , G06F8/443 , G06F9/30032 , G06F9/30094 , G06F9/30098 , G06F9/3013 , G06F9/30181 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.
摘要翻译：涉及移动消除的数据处理操作中标志跟踪的系统和方法。示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

6. 发明授权

US09354875B2 Enhanced loop streaming detector to drive logic optimization 有权
标题翻译：增强循环流检测器驱动逻辑优化
公开(公告)号：US09354875B2
公开(公告)日：2016-05-31
申请号：US13728273
申请日：2012-12-27
申请人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
发明人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/3885
摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.
摘要翻译：在处理器中提供增强的循环流检测机制以降低功耗。处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

7. 发明申请

US20150006868A1 MINIMIZING BANDWITH TO COMPRESS OUTPUT STREAM IN INSTRUCTION TRACING SYSTEMS 有权
标题翻译：在指令跟踪系统中最小化压缩输出流
公开(公告)号：US20150006868A1
公开(公告)日：2015-01-01
申请号：US13930501
申请日：2013-06-28
申请人： Ilya Wagner , Matthew C. Merten , Frank Binns , Christine E. Wang , Mayank Bomb , Tong Li , Thilo Schmitt , MD A. Rahman
发明人： Ilya Wagner , Matthew C. Merten , Frank Binns , Christine E. Wang , Mayank Bomb , Tong Li , Thilo Schmitt , MD A. Rahman
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/81
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.
摘要翻译：根据本文公开的实施例，提供了用于最小化带宽以压缩指令跟踪系统的输出流的系统和方法。例如，该方法可以包括将IT模块的跟踪中的当前指令识别为条件分支（CB）指令。该方法包括执行以下步骤：生成包括具有CB指令的结果的指示的字节模式的CB分组，或者将CB指令的结果的指示添加到现有CB分组的字节模式。该方法包括当跟踪中的后续指令不是CB指令时产生分组。该分组与CB分组不同。该方法还包括当分组可延迟时将分组添加到延迟队列中。该方法还包括将后续的延迟分组的CB分组输出到分组日志中。

8. 发明申请

US20140337604A1 MINIMIZING BANDWIDTH TO TRACK RETURN TARGETS BY AN INSTRUCTION TRACING SYSTEM 有权
标题翻译：通过指令跟踪系统最小化带宽跟踪返回目标
公开(公告)号：US20140337604A1
公开(公告)日：2014-11-13
申请号：US13890654
申请日：2013-05-09
申请人： Beeman C. Strong , Matthew C. Merten , Tong Li
发明人： Beeman C. Strong , Matthew C. Merten , Tong Li
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3806 , G06F9/3857 , G06F11/3476 , G06F11/3636
摘要： A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the disclosure an instruction fetch unit comprising a return stack buffer (RSB) to predict a target address of a return (RET) instruction corresponding to a call (CALL) instruction. The processing device further includes a retirement unit comprising an instruction tracing module to initiate instruction tracing for instructions executed by the processing device, determine whether the target address of the RET instruction was mispredicted, determine a value of call depth counter (CDC) maintained by the instruction tracing module, and when the target address of the RET instruction was not mispredicted and when the value of the CDC is greater than zero, generate an indication that the RET instruction branches to a next linear instruction after the corresponding CALL instruction.
摘要翻译：公开了一种通过指令跟踪系统实现最小化带宽以跟踪返回目标的处理设备。本公开的处理装置包括一个指令提取单元，该单元包括用于预测与一个调用（CALL）指令相对应的返回（RET）指令的目标地址的返回栈缓冲器（RSB）。所述处理装置还包括退出单元，所述退出单元包括指令跟踪模块，用于启动由所述处理设备执行的指令的指令跟踪，确定所述RET指令的目标地址是否被错误预测，确定由所述处理设备维护的所述呼叫深度计数器指令跟踪模块，并且当RET指令的目标地址未被错误预测时，并且当CDC的值大于零时，生成指令在相应的CALL指令之后分支到下一个线性指令。

9. 发明申请

US20140201505A1 PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR 审中-公开
标题翻译：在多处理器中基于预测的螺纹选择
公开(公告)号：US20140201505A1
公开(公告)日：2014-07-17
申请号：US13997837
申请日：2012-03-30
申请人： Matthew C. Merten , Tong Li , Vijaykumar B. Kadgi , Srikanth T. Srinivasan , Christine E. Wang
发明人： Matthew C. Merten , Tong Li , Vijaykumar B. Kadgi , Srikanth T. Srinivasan , Christine E. Wang
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3851 , G06F9/4843 , Y02D10/24
摘要： A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions.
摘要翻译：处理器包括一个或多个执行单元，用于执行多个线程的指令和与执行单元耦合的线程控制逻辑，以基于当前周期的指令的准备就绪来预测多个线程中的第一个线程是否准备好在当前周期中进行选择在一个或多个先前循环中的第一线程，以基于所述一个或多个先前循环中的第二线程的指令的准备来预测多个线程中的第二线程是否准备好在当前周期中进行选择，并且选择基于预测的当前循环中的第一和第二个线程。

10. 发明申请

US20220134495A1 ENGRAVING FIXTURE FOR MULTIPLE SERIALLY ARRANGED OBJECTS 有权
公开(公告)号：US20220134495A1
公开(公告)日：2022-05-05
申请号：US17089422
申请日：2020-11-04
申请人： Tong Li
发明人： Tong Li
IPC分类号： B23Q1/54
摘要： A fixture for facilitating the serial engraving of a plurality of cylindrical objects such as glasses or mugs mounted on individual serially arranged stations along a master base plate. Each station includes a drive structure and, spaced therefrom, a passive support structure. The two structures in each station can be gang-adjusted for object length. In addition, the support structures can be height-adjusted to level the engraved surfaces of tapered objects. All of the drive structures include drive wheel pairs and all are driven by a single stepper motor via a single shaft and individual belt and pulley systems.

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