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1. 发明授权

US11080045B2 Addition instructions with independent carry chains 有权
公开(公告)号：US11080045B2
公开(公告)日：2021-08-03
申请号：US13993483
申请日：2011-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
IPC分类号： G06F9/30 , G06F9/38
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

2. 发明申请

US20140013086A1 ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS 审中-公开
标题翻译：附加说明与独立的携带链
公开(公告)号：US20140013086A1
公开(公告)日：2014-01-09
申请号：US13993483
申请日：2011-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30094 , G06F9/3838
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.
摘要翻译：提供了彼此之间没有数据依赖性的多个附加指令。第一加法指令将其进位输出存储在标志寄存器的第一标志中，而不修改标志寄存器中的第二标志。第二加法指令将其进位输出存储在标志寄存器的第二标志中，而不修改标志寄存器中的第一个标志。

3. 发明申请

US20140195790A1 PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
标题翻译：具有分支机构错误预测的第二个执行单元的处理程序
公开(公告)号：US20140195790A1
公开(公告)日：2014-07-10
申请号：US13994676
申请日：2011-12-28
申请人： Matthew C. Merten , Avinash Sodani , Sean P. Mirkes , Vijaykumar B. Kadgi , Bambang Sutanto , Chia Yin Kevin Lai , Morris Marden , Alexandre J. Farcy
发明人： Matthew C. Merten , Avinash Sodani , Sean P. Mirkes , Vijaykumar B. Kadgi , Bambang Sutanto , Chia Yin Kevin Lai , Morris Marden , Alexandre J. Farcy
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.
摘要翻译：次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而初级JEU不处理分支。此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

4. 发明申请

US20140156977A1 ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
标题翻译：启用和禁用分支机构错误预测的第二个执行单位
公开(公告)号：US20140156977A1
公开(公告)日：2014-06-05
申请号：US13994699
申请日：2011-12-28
申请人： Mark J. Dechene , Matthew C. Merten , Sean P. Mirkes
发明人： Mark J. Dechene , Matthew C. Merten , Sean P. Mirkes
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/3844 , G06F9/3851 , G06F9/3885
摘要： Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.
摘要翻译：描述了在微处理器中启用和/或禁用辅助跳转执行单元（JEU）的技术。次级JEU被并入微处理器以与主JEU同时操作，并且能够在多个分支上处理同时的分支错误预测。次级JEU的激活和停用可以由压力计数器或置信计数器来控制。压力计数器机构增加在处理器内执行的每个分支操作的计数，并在每个周期期间将计数减去衰减值。置信度计数机制增加每个正确预测分支的计数，并减少每个错误预测的计数。当计数器超过激活阈值时，每个计数器发出一个激活组件，例如端口绑定硬件组件，开始将微操作绑定到辅助JEU。计数器机制可能是线程不可知或线程特定的。

5. 发明申请

US20130205119A1 INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS 有权
标题翻译：指令和逻辑测试交易执行状态
公开(公告)号：US20130205119A1
公开(公告)日：2013-08-08
申请号：US13538951
申请日：2012-06-29
申请人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
发明人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
IPC分类号： G06F9/46
CPC分类号： G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

6. 发明授权

US09268596B2 Instruction and logic to test transactional execution status 有权
标题翻译：测试事务执行状态的指令和逻辑
公开(公告)号：US09268596B2
公开(公告)日：2016-02-23
申请号：US13538951
申请日：2012-06-29
申请人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
发明人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
IPC分类号： G06F9/46 , G06F9/38 , G06F9/30
CPC分类号： G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

7. 发明申请

US20150032998A1 METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
标题翻译：方法，装置和系统的交互式分析控制指令
公开(公告)号：US20150032998A1
公开(公告)日：2015-01-29
申请号：US13997243
申请日：2012-02-02
申请人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Alexandre J. Farcy , Bret L. Toll , Robert S. Chappell , Matthew C. Merten , Rajesh S. Parthasarathy , Per Hammarlund
发明人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Alexandre J. Farcy , Bret L. Toll , Robert S. Chappell , Matthew C. Merten , Rajesh S. Parthasarathy , Per Hammarlund
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3851 , G06F9/3859
摘要： An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.
摘要翻译：这里描述了一种用于提供猜测控制指令的装置和方法。提供xAcquire和xRelease指令来定义关键部分。在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。此外，xBegin和xEnd在指令集架构（ISA）中类似地提供以定义事务代码区域。此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

8. 发明申请

US20140189306A1 ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION 有权
标题翻译：增强环路检测器驱动逻辑优化
公开(公告)号：US20140189306A1
公开(公告)日：2014-07-03
申请号：US13728273
申请日：2012-12-27
申请人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
发明人： Matthew C. Merten , Justin M. Deinlein , Yury N. Ilin , Alexandre J. Farcy , Tong Li , Srikanth T. Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/3885
摘要： An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.
摘要翻译：在处理器中提供增强的循环流检测机制以降低功耗。处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

9. 发明授权

US09442729B2 Minimizing bandwidth to track return targets by an instruction tracing system 有权
标题翻译：最小化带宽以通过指令跟踪系统跟踪返回目标
公开(公告)号：US09442729B2
公开(公告)日：2016-09-13
申请号：US13890654
申请日：2013-05-09
申请人： Beeman C. Strong , Matthew C. Merten , Tong Li
发明人： Beeman C. Strong , Matthew C. Merten , Tong Li
IPC分类号： G06F9/30 , H04L29/06 , G06F9/38 , G06F11/36 , G06F11/34
CPC分类号： G06F9/30145 , G06F9/3806 , G06F9/3857 , G06F11/3476 , G06F11/3636
摘要： A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the disclosure an instruction fetch unit comprising a return stack buffer (RSB) to predict a target address of a return (RET) instruction corresponding to a call (CALL) instruction. The processing device further includes a retirement unit comprising an instruction tracing module to initiate instruction tracing for instructions executed by the processing device, determine whether the target address of the RET instruction was mispredicted, determine a value of call depth counter (CDC) maintained by the instruction tracing module, and when the target address of the RET instruction was not mispredicted and when the value of the CDC is greater than zero, generate an indication that the RET instruction branches to a next linear instruction after the corresponding CALL instruction.
摘要翻译：公开了一种通过指令跟踪系统实现最小化带宽以跟踪返回目标的处理设备。本公开的处理装置包括一个指令提取单元，该单元包括用于预测与一个调用（CALL）指令相对应的返回（RET）指令的目标地址的返回栈缓冲器（RSB）。所述处理装置还包括退出单元，所述退出单元包括指令跟踪模块，用于启动由所述处理设备执行的指令的指令跟踪，确定所述RET指令的目标地址是否被错误预测，确定由所述处理设备维护的所述呼叫深度计数器指令跟踪模块，并且当RET指令的目标地址未被错误预测时，并且当CDC的值大于零时，生成指令在相应的CALL指令之后分支到下一个线性指令。

10. 发明授权

US09292288B2 Systems and methods for flag tracking in move elimination operations 有权
标题翻译：移动消除操作中标志跟踪的系统和方法
公开(公告)号：US09292288B2
公开(公告)日：2016-03-22
申请号：US13861009
申请日：2013-04-11
申请人： Vijaykumar B. Kadgi , Jeremy R. Anderson , James D. Hadley , Tong Li , Matthew C. Merten
发明人： Vijaykumar B. Kadgi , Jeremy R. Anderson , James D. Hadley , Tong Li , Matthew C. Merten
IPC分类号： G06F9/30 , G06F9/45 , G06F9/38
CPC分类号： G06F9/30105 , G06F8/443 , G06F9/30032 , G06F9/30094 , G06F9/30098 , G06F9/3013 , G06F9/30181 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.
摘要翻译：涉及移动消除的数据处理操作中标志跟踪的系统和方法。示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

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