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1. 发明申请

US20120229313A1 ANALOG TO DIGITAL CONVERTER CIRCUIT 有权
标题翻译：模拟到数字转换器电路
公开(公告)号：US20120229313A1
公开(公告)日：2012-09-13
申请号：US13232442
申请日：2011-09-14
申请人： Sai-Weng SIN , He-Gong WEI , Franco MALOBERTI , Li DING , Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Seng-Pan U , Rui Paulo da Silva MARTINS
发明人： Sai-Weng SIN , He-Gong WEI , Franco MALOBERTI , Li DING , Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Seng-Pan U , Rui Paulo da Silva MARTINS
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/1215 , H03M1/164 , H03M1/468
摘要： The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design
摘要翻译：本发明提供一种包括两个时间交错的逐次逼近寄存器（SAR）ADC的模数转换器（ADC）电路。两个时间交织的SAR ADC中的每一个包括第一级SAR子ADC，残差放大器，第二级SAR子ADC和数字纠错逻辑。剩余放大器在时间交织路径之间共享，具有减小的增益并且在子阈值中操作以实现功率有效设计

2. 发明授权

US08427355B2 Time-interleaved pipelined-SAR analog to digital converter with low power consumption 有权
标题翻译：时间交错流水线SAR模数转换器，功耗低
公开(公告)号：US08427355B2
公开(公告)日：2013-04-23
申请号：US13232442
申请日：2011-09-14
申请人： Sai-Weng Sin , Li Ding , Yan Zhu , He-Gong Wei , Chi-Hang Chan , U-Fat Chio , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： Sai-Weng Sin , Li Ding , Yan Zhu , He-Gong Wei , Chi-Hang Chan , U-Fat Chio , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/38
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/1215 , H03M1/164 , H03M1/468
摘要： An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
摘要翻译：包括两个时间交错的逐次逼近寄存器（SAR）ADC的模数转换器（ADC）电路。两个时间交织的SAR ADC中的每一个包括第一级SAR子ADC，残差放大器，第二级SAR子ADC和数字纠错逻辑。剩余放大器在时间交织路径之间共享，具有减小的增益并且在子阈值中操作以实现功率有效设计。

3. 发明申请

US20120306679A1 N-BITS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTING CIRCUIT 有权
标题翻译： N-bit连续逼近寄存器模拟到数字转换电路
公开(公告)号：US20120306679A1
公开(公告)日：2012-12-06
申请号：US13150508
申请日：2011-06-01
申请人： Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Sai-Weng SIN , Seng-Pan U , Rui Paulo Da Silva MARTINS , Franco MALOBERTI
发明人： Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Sai-Weng SIN , Seng-Pan U , Rui Paulo Da Silva MARTINS , Franco MALOBERTI
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/466
摘要： The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.
摘要翻译：本发明提供一种n位逐次逼近寄存器（SAR）模数转换（ADC）电路，包括：n位SAR控制逻辑，包括DACp阵列和采样电容器CSp的p型电容器网络包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器，其中电源和接地直接连接到p型电容器网络和n型电容器网络，而不使用由p型电容器网络和n型电容器网络产生的参考电压参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器，n个位寄存器和一个开关逻辑。比较器包括第一前置放大器，第二前置放大器和动态锁存器。替代方案，比较器包括四输入前置放大器和动态锁存器。

4. 发明授权

US08344931B2 N-bits successive approximation register analog-to-digital converting circuit 有权
标题翻译： N位逐次逼近寄存器模数转换电路
公开(公告)号：US08344931B2
公开(公告)日：2013-01-01
申请号：US13150508
申请日：2011-06-01
申请人： Yan Zhu , Chi-Hang Chan , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo Da Silva Martins , Franco Maloberti
发明人： Yan Zhu , Chi-Hang Chan , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo Da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/466
摘要： The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.
摘要翻译：本发明提供一种n位逐次逼近寄存器（SAR）模数转换（ADC）电路，包括：n位SAR控制逻辑，包括DACp阵列和采样电容器CSp的p型电容器网络包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器，其中电源和接地直接连接到p型电容器网络和n型电容器网络，而不使用由p型电容器网络和n型电容器网络产生的参考电压参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器，n个位寄存器和一个开关逻辑。比较器包括第一前置放大器，第二前置放大器和动态锁存器。替代方案，比较器包括四输入前置放大器和动态锁存器。

5. 发明授权

US08466823B2 Cascade analog-to-digital converting system 有权
标题翻译：级联模数转换系统
公开(公告)号：US08466823B2
公开(公告)日：2013-06-18
申请号：US13198856
申请日：2011-08-05
申请人： U-Fat Chio , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： U-Fat Chio , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/0695 , H03M1/365 , H03M1/46
摘要： A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
摘要翻译：公开了一种使用两步转换的新型模 - 数转换器（ADC）系统。 ADC系统能够实现高采样率，低功耗和低复杂度。新提出的ADC是通过使用具有低功耗和低采样率的逐次逼近（SA）ADC级联具有高采样率和低分辨率的闪存ADC来形成的。

6. 发明申请

US20120194364A1 ANALOG-TO-DIGITAL CONVERTING SYSTEM 有权
标题翻译：模拟数字转换系统
公开(公告)号：US20120194364A1
公开(公告)日：2012-08-02
申请号：US13198856
申请日：2011-08-05
申请人： U-Fat CHIO , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： U-Fat CHIO , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/0695 , H03M1/365 , H03M1/46
摘要： A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
摘要翻译：公开了一种使用两步转换的新型模 - 数转换器（ADC）系统。 ADC系统能够实现高采样率，低功耗和低复杂度。新提出的ADC是通过使用具有低功耗和低采样率的逐次逼近（SA）ADC级联具有高采样率和低分辨率的闪存ADC来形成的。

7. 发明授权

US08441295B2 Delay generator 有权
标题翻译：延迟发生器
公开(公告)号：US08441295B2
公开(公告)日：2013-05-14
申请号：US13289229
申请日：2011-11-04
申请人： He-Gong Wei , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins
发明人： He-Gong Wei , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins
IPC分类号： H03H11/06
CPC分类号： H03K5/133 , H03K5/14
摘要： A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.
摘要翻译：延迟发生器包括：用于提供电流的电流源; 连接到电流源的第一延迟部分，包括至少多个反相器和具有第一电容的第一电容器; 以及连接到所述电流源的第二延迟部分，包括至少多个反相器和具有第二电容的第二电容器，其中所述第一电容与所述第二电容相同，其中所述第一延迟部分产生第一延迟，第一电容器的放电，其中第二延迟部分通过对第二电容器进行充电来产生第二延迟，并且其中由延迟发生器产生的总延迟通过第一延迟和第二延迟的相加获得。

8. 发明申请

US20120286840A1 DELAY GENERATOR 有权
标题翻译：延时发电机
公开(公告)号：US20120286840A1
公开(公告)日：2012-11-15
申请号：US13289229
申请日：2011-11-04
申请人： He-Gong Wei , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins
发明人： He-Gong Wei , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K5/14
摘要： A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.
摘要翻译：延迟发生器包括：用于提供电流的电流源; 连接到电流源的第一延迟部分，包括至少多个反相器和具有第一电容的第一电容器; 以及连接到所述电流源的第二延迟部分，包括至少多个反相器和具有第二电容的第二电容器，其中所述第一电容与所述第二电容相同，其中所述第一延迟部分产生第一延迟，第一电容器的放电，其中第二延迟部分通过对第二电容器进行充电来产生第二延迟，并且其中由延迟发生器产生的总延迟通过第一延迟和第二延迟的相加获得。

9. 发明授权

US08019290B2 Two-step channel selection for wireless transmitter front-ends 有权
标题翻译：无线发射机前端的两步通道选择
公开(公告)号：US08019290B2
公开(公告)日：2011-09-13
申请号：US12203837
申请日：2008-09-03
申请人： Pui-In Mak , Seng-Pan U , Rui Paulo da Silva Martins
发明人： Pui-In Mak , Seng-Pan U , Rui Paulo da Silva Martins
IPC分类号： H04B1/02 , H04B1/04 , H01Q11/12
CPC分类号： H03H11/1291 , H03D3/007 , H04B1/28
摘要： A reconfigurable multimode transmitter is disclosed, operating in accordance with a two-step channel selection. The first step provides for a fine channel selection and upconversion of a desired channel to either positive or negative IF. The second step is a coarse channel selection and upconversion of a desired channel to the RF. The receiver and transmitter can be used in a transceiver.
摘要翻译：公开了可重新配置的多模式发射器，其根据两步通道选择进行操作。第一步提供精确的通道选择和所需通道的上变频到正或负IF。第二步是对RF的期望信道的粗略信道选择和上变频。接收机和发射机可以用在收发器中。

10. 发明申请

US20080318534A1 TWO-STEP CHANNEL SELECTION FOR WIRELESS TRANSMITTER FRONT-ENDS 有权
标题翻译：用于无线发射机前端的两步通道选择
公开(公告)号：US20080318534A1
公开(公告)日：2008-12-25
申请号：US12203837
申请日：2008-09-03
申请人： Pui-In MAK , Seng-Pan U , Rui Paulo da Silva MARTINS
发明人： Pui-In MAK , Seng-Pan U , Rui Paulo da Silva MARTINS
IPC分类号： H04B1/02
CPC分类号： H03H11/1291 , H03D3/007 , H04B1/28
摘要： A reconfigurable multimode transmitter is disclosed, operating in accordance with a two-step channel selection. The first step provides for a fine channel selection and upconversion of a desired channel to either positive or negative IF. The second step is a coarse channel selection and upconversion of a desired channel to the RF. The receiver and transmitter can be used in a transceiver.
摘要翻译：公开了可重新配置的多模式发射器，其根据两步通道选择进行操作。第一步提供精确的通道选择和所需通道的上变频到正或负IF。第二步是对RF的期望信道的粗略信道选择和上变频。接收机和发射机可以用在收发器中。

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