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    • 9. 发明授权
    • N-bits successive approximation register analog-to-digital converting circuit
    • N位逐次逼近寄存器模数转换电路
    • US08344931B2
    • 2013-01-01
    • US13150508
    • 2011-06-01
    • Yan ZhuChi-Hang ChanU-Fat ChioSai-Weng SinSeng-Pan URui Paulo Da Silva MartinsFranco Maloberti
    • Yan ZhuChi-Hang ChanU-Fat ChioSai-Weng SinSeng-Pan URui Paulo Da Silva MartinsFranco Maloberti
    • H03M1/12
    • H03M1/002H03M1/466
    • The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.
    • 本发明提供一种n位逐次逼近寄存器(SAR)模数转换(ADC)电路,包括:n位SAR控制逻辑,包括DACp阵列和采样电容器CSp的p型电容器网络 包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器,其中电源和接地直接连接到p型电容器网络和n型电容器网络,而不使用由p型电容器网络和n型电容器网络产生的参考电压 参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器,n个位寄存器和一个开关逻辑。 比较器包括第一前置放大器,第二前置放大器和动态锁存器。 替代方案,比较器包括四输入前置放大器和动态锁存器。