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1. 发明申请

US20100238599A1 Power Supply Equalization Circuit Using Distributed High-Voltage and Low-Voltage Shunt Circuits 有权
标题翻译：使用分布式高压和低压分流电路的电源均衡电路
公开(公告)号：US20100238599A1
公开(公告)日：2010-09-23
申请号：US12406705
申请日：2009-03-18
申请人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
发明人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
IPC分类号： H02H9/04
CPC分类号： H03K19/00315
摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.
摘要翻译：描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压或其他过大的电流条件的影响。每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。实施例的保护电路包括高电压IO引脚，降压网络，以将IO引脚上的高电压降低到浮置电压轨上的低电压电平;耦合在浮动电源轨和地之间的第一分流电路，耦合在浮动电源轨和低电压电源轨之间的均衡器电路，以及通过低压供电轨耦合到均衡器电路的第二分流电路。

2. 发明授权

US08102633B2 Power supply equalization circuit using distributed high-voltage and low-voltage shunt circuits 有权
标题翻译：电源均衡电路采用分布式高压和低压分流电路
公开(公告)号：US08102633B2
公开(公告)日：2012-01-24
申请号：US12406705
申请日：2009-03-18
申请人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
发明人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22
CPC分类号： H03K19/00315
摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.
摘要翻译：描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压或其他过大的电流条件的影响。每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。实施例的保护电路包括高电压IO引脚，降压网络，以将IO引脚上的高电压降低到浮置电压轨上的低电压电平;耦合在浮动电源轨和地之间的第一分流电路，耦合在浮动电源轨和低电压电源轨之间的均衡器电路，以及通过低压供电轨耦合到均衡器电路的第二分流电路。

3. 发明授权

US08102632B2 Electrostatic discharge power clamp trigger circuit using low stress voltage devices 有权
标题翻译：静电放电电源钳位触发电路采用低应力电压器件
公开(公告)号：US08102632B2
公开(公告)日：2012-01-24
申请号：US12406684
申请日：2009-03-18
申请人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
发明人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H03K19/00315
摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.
摘要翻译：描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压的影响。每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。实施例的保护电路包括高电压IO引脚接口，耦合到IO引脚的电压降网络，并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平，耦合在所述电压降网络和接地端子之间的NMOS分流晶体管，以及耦合到所述NMOS分流晶体管的触发电路，以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。

4. 发明申请

US20100238598A1 Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices 有权
标题翻译：使用低应力电压器件的静电放电电源钳位触发电路
公开(公告)号：US20100238598A1
公开(公告)日：2010-09-23
申请号：US12406684
申请日：2009-03-18
申请人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
发明人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
IPC分类号： H02H9/04 , G06F17/00
CPC分类号： H03K19/00315
摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.
摘要翻译：描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压的影响。每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。实施例的保护电路包括高电压IO引脚接口，耦合到IO引脚的电压降网络，并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平，耦合在所述电压降网络和接地端子之间的NMOS分流晶体管，以及耦合到所述NMOS分流晶体管的触发电路，以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。

5. 发明授权

US07256617B2 Method and apparatus to linearize output buffer and on-chip termination 有权
标题翻译：线性化输出缓冲器和片上终止的方法和装置
公开(公告)号：US07256617B2
公开(公告)日：2007-08-14
申请号：US10387723
申请日：2003-03-13
申请人： Priya Ananthanarayanan , Samudyatha Suryanarayana
发明人： Priya Ananthanarayanan , Samudyatha Suryanarayana
IPC分类号： H03K19/094
CPC分类号： H03K17/166
摘要： A driver circuit that outputs a data signal uses feedback of the data signal to the driver circuit to modulate a drive strength of the driver circuit. The driver circuit has a pull-up driver stage and a pull-down driver stage. The pull-up driver stage uses a pull-up control circuit to modulate a drive strength of the pull-up driver stage dependent on a voltage of the data signal. The pull-down driver stage uses a pull-down control circuit to modulate a drive strength of the pull-down driver stage dependent on the voltage of the data signal.
摘要翻译：输出数据信号的驱动电路使用数据信号的反馈到驱动电路来调制驱动电路的驱动强度。驱动电路具有上拉驱动级和下拉驱动级。上拉驱动级使用上拉控制电路根据数据信号的电压来调制上拉驱动级的驱动强度。下拉驱动级使用下拉控制电路根据数据信号的电压来调制下拉驱动级的驱动强度。

6. 发明授权

US06762623B2 High-resolution single-ended source-synchronous receiver 有权
标题翻译：高分辨率单端源同步接收机
公开(公告)号：US06762623B2
公开(公告)日：2004-07-13
申请号：US10320148
申请日：2002-12-16
申请人： Samudyatha Suryanarayana , Aninda K. Roy
发明人： Samudyatha Suryanarayana , Aninda K. Roy
IPC分类号： H03K19082
CPC分类号： H04L25/0292
摘要： Disclosed are novel methods and apparatus for efficiently providing high-resolution single-ended source synchronous receivers. In an embodiment of the present invention, a source-synchronous receiver is disclosed. The receiver includes: a first amplifier to receive a clock signal and a data signal, the first amplifier providing a first output signal; a second amplifier to receive a complementary clock signal and the data signal, the second amplifier providing a second output signal; a third amplifier to receive the clock signal and the data signal, the third amplifier providing a third output signal, the second and third output signals being combined to provide a fifth output; and a fourth amplifier to receive the complementary clock signal and the data signal, the fourth amplifier providing a fourth output signal, the first and fourth output signals being combined to provide a sixth output signal.
摘要翻译：公开了用于有效提供高分辨率单端源同步接收机的新颖方法和装置。在本发明的实施例中，公开了一种源同步接收机。所述接收机包括：第一放大器，用于接收时钟信号和数据信号，所述第一放大器提供第一输出信号; 第二放大器，用于接收互补时钟信号和所述数据信号，所述第二放大器提供第二输出信号; 第三放大器，用于接收所述时钟信号和所述数据信号，所述第三放大器提供第三输出信号，所述第二和第三输出信号被组合以提供第五输出; 以及第四放大器，用于接收所述互补时钟信号和所述数据信号，所述第四放大器提供第四输出信号，所述第一和第四输出信号被组合以提供第六输出信号。

7. 发明授权

US06747485B1 Sense amplifier type input receiver with improved clk to Q 失效
标题翻译：感应放大器型输入接收器，具有改进的clk到Q
公开(公告)号：US06747485B1
公开(公告)日：2004-06-08
申请号：US09605264
申请日：2000-06-28
申请人： Samudyatha Suryanarayana , Gajendra P. Singh
发明人： Samudyatha Suryanarayana , Gajendra P. Singh
IPC分类号： H03F345
CPC分类号： G11C7/1087 , G11C7/065 , G11C7/1078
摘要： A sense amplifier type input receiver includes a differential receiver circuit operatively coupled to an output stage. The output stage includes a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output. The output stage may include a first pass gate operatively coupled between the first differential output and an output of the output stage, a second pass gate operatively coupled between the second differential output and the pass gate enabled latch, and the pass gate enabled latch may be operatively coupled to the output of the output stage. A first clock signal and second clock signal may be coupled to the first pass gate to enable passing of the first differential output to the output of the output stage, the first and second clock signals may be coupled to the second pass gate to enable passing of the second differential output to the pass gate enabled latch, and the first and second clocks signal coupled to a pass gate of the pass gate enabled latch to enable operation of the pass gate enabled latch. A first inverter may be operatively coupled between the first differential output and the first pass gate, a second inverter operatively coupled between the second differential output and the second pass gate, and a third inverter operatively coupled to the output of the output stage.
摘要翻译：感测放大器型输入接收机包括可操作地耦合到输出级的差分接收器电路。输出级包括通过闸门使能的锁存器。差分接收器电路可以输出第一差分输出和第二差分输出。输出级可以包括可操作地耦合在第一差分输出和输出级的输出之间的第一通过门，可操作地耦合在第二差分输出和通过栅极使能的锁存器之间的第二通道门，并且通通门使能的锁存器可以是可操作地耦合到输出级的输出。第一时钟信号和第二时钟信号可以耦合到第一传递门，以使得能够将第一差分输出传递到输出级的输出，第一和第二时钟信号可以耦合到第二通道门，以使所述第二差分输出到所述通过门使能的锁存器，并且所述第一和第二时钟信号耦合到所述通过栅极使能的锁存器的通过栅极以使能所述通过栅极使能的锁存器的操作。第一反相器可以可操作地耦合在第一差分输出和第一通过栅极之间，第二反相器可操作地耦合在第二差分输出和第二通过栅极之间，第三反相器可操作地耦合到输出级的输出端。

8. 发明授权

US06756824B2 Self-biased driver amplifiers for high-speed signaling interfaces 有权
标题翻译：用于高速信号接口的自偏置驱动器放大器
公开(公告)号：US06756824B2
公开(公告)日：2004-06-29
申请号：US10292261
申请日：2002-11-12
申请人： Aninda K. Roy , Samudyatha Suryanarayana
发明人： Aninda K. Roy , Samudyatha Suryanarayana
IPC分类号： H03B100
CPC分类号： H03K19/00384 , H03K19/00323
摘要： Disclosed are novel methods and apparatus for efficiently providing self-biased driver amplifiers for high-speed signaling interfaces. In an embodiment of the present invention, a self-biased amplifier driver is disclosed. The driver includes a sensing circuit to sense a presence of noise in a power supply signal. The sensing circuit may include a current source to adjust an output signal of the sensing circuit in accordance with the power supply noise. The driver may further include: an amplifier coupled to the sensing circuit to amplify the sensing circuit output signal, a pre-driver to receive a data signal, and a driver coupled to the amplifier and the pre-driver to receive an amplifier output signal and a pre-driver output signal.
摘要翻译：公开了用于高速提供用于高速信令接口的自偏置驱动器放大器的新颖方法和装置。在本发明的实施例中，公开了一种自偏置放大器驱动器。驱动器包括用于感测电源信号中的噪声的感测电路。感测电路可以包括电流源，以根据电源噪声来调节感测电路的输出信号。驱动器还可以包括：耦合到感测电路以放大感测电路输出信号的放大器，用于接收数据信号的预驱动器和耦合到放大器和预驱动器的驱动器以接收放大器输出信号的放大器，预驱动器输出信号。

9. 发明授权

US06831487B2 Pattern based dynamic drive current balancing for data transmission 有权
标题翻译：基于模式的动态驱动电流平衡数据传输
公开(公告)号：US06831487B2
公开(公告)日：2004-12-14
申请号：US10393303
申请日：2003-03-20
申请人： Samudyatha Suryanarayana , Priya Ananthanarayanan
发明人： Samudyatha Suryanarayana , Priya Ananthanarayanan
IPC分类号： H03B2100
CPC分类号： H03K17/164
摘要： A driver stage uses a primary driver and a secondary driver to balance drive current when transmitting a new data bit different than bits consecutively transmitted immediately previous to the new data bit. The primary driver activates one of a pull-down device and a pull-up device whenever transmitting a data bit. The secondary driver activates one of its pull-down device and a pull-up device when two or more consecutive are detected to be transmitted. In this case, current flow of the driver stage induced by the first of the consecutive bits is reduced by the secondary driver.
摘要翻译：驱动器级使用主驱动器和次驱动器来平衡驱动电流，以便在发送与紧随新数据位之前连续发送的位不同的新数据位时。每当发送数据位时，主驱动器激活下拉器件和上拉器件中的一个。当检测到两个或多个连续的传输时，辅助驱动器激活其下拉装置中的一个和上拉装置。在这种情况下，由第二驱动器减少由第一连续位引起的驱动级的电流。

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