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1. 发明申请

US20100238599A1 Power Supply Equalization Circuit Using Distributed High-Voltage and Low-Voltage Shunt Circuits 有权
标题翻译：使用分布式高压和低压分流电路的电源均衡电路
公开(公告)号：US20100238599A1
公开(公告)日：2010-09-23
申请号：US12406705
申请日：2009-03-18
申请人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
发明人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
IPC分类号： H02H9/04
CPC分类号： H03K19/00315
摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.
摘要翻译：描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压或其他过大的电流条件的影响。每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。实施例的保护电路包括高电压IO引脚，降压网络，以将IO引脚上的高电压降低到浮置电压轨上的低电压电平;耦合在浮动电源轨和地之间的第一分流电路，耦合在浮动电源轨和低电压电源轨之间的均衡器电路，以及通过低压供电轨耦合到均衡器电路的第二分流电路。

2. 发明申请

US20090168854A1 De-Emphasis Circuit for a Voltage Mode Driver Used to Communicate Via a Differential Communication Link 有权
标题翻译：用于通过差分通信链路进行通信的电压模式驱动器的去加重电路
公开(公告)号：US20090168854A1
公开(公告)日：2009-07-02
申请号：US12032741
申请日：2008-02-18
申请人： Yikai Liang , Arvind Bomdica , Min Xu , Ming-Ju Ml. Lee
发明人： Yikai Liang , Arvind Bomdica , Min Xu , Ming-Ju Ml. Lee
IPC分类号： H04B1/40 , H04L27/04
CPC分类号： H03K19/0019 , H04L1/08 , H04L25/0272 , H04L25/0286
摘要： A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.
摘要翻译：用于去强调通过差分通信链路发送的信息的电路包括电压模式差分电路和双向电流源电路。电压模式差分电路包括第一和第二输出端子。电压模式差分电路响应于差分输入电压经由第一输出端子经由第二输出端子提供第一电压和第二电压。双向电流源电路可操作地耦合在第一和第二端子之间。双向电流源电路基于第一和第二电压选择性地在第一和第二端子之间的第一和第二方向上提供电流。

3. 发明申请

US20130147554A1 LOW-POWER HIGH-GAIN MULTISTAGE COMPARATOR CIRCUIT 有权
标题翻译：低功耗高增益多电路比较器电路
公开(公告)号：US20130147554A1
公开(公告)日：2013-06-13
申请号：US13316488
申请日：2011-12-10
申请人： Xin Liu , Arvind Bomdica , Yikai Liang
发明人： Xin Liu , Arvind Bomdica , Yikai Liang
IPC分类号： H03F3/45
CPC分类号： H03F3/3022 , H03F3/45183 , H03F2203/45644 , H03F2203/45674 , H03F2203/45676
摘要： A method is provided for receiving a differential signal pair input at a first circuit stage and converting the differential signal pair input to a single-ended signal at a second circuit stage. The method also provides for receiving an output of the first circuit stage and an output of the second stage at a third circuit stage and transmitting an amplified signal output from the third circuit stage. The method allows for a 60 dB signal gain or more. A circuit is also provided that includes multiple circuit stages that can provide signal gain to an input differential signal pair. The circuit converts the differential pair into a single-ended signal and transmits the amplified signal as an output. The circuit provides the signal gain without using a current mirror. A computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus is also provided.
摘要翻译：提供一种用于接收在第一电路级输入的差分信号对，并在第二电路级将差分信号对输入转换为单端信号的方法。该方法还提供在第三电路级接收第一电路级的输出和第二级的输出，并且传输从第三电路级输出的放大信号。该方法允许60dB的信号增益或更多。还提供了一种电路，其包括可向输入差分信号对提供信号增益的多个电路级。电路将差分对转换为单端信号，并将放大的信号作为输出发送。该电路在不使用电流镜的情况下提供信号增益。还提供了一种用于适配制造设备以创建设备的数据编码的计算机可读存储设备。

4. 发明授权

US08149024B2 Dual function voltage and current mode differential driver 有权
标题翻译：双功能电压和电流模式差分驱动器
公开(公告)号：US08149024B2
公开(公告)日：2012-04-03
申请号：US12633174
申请日：2009-12-08
申请人： Xin Liu , Arvind Bomdica , Yikai Liang , Ming-Ju Edward Lee , Rohit Rathi , Jinyung Namkoong
发明人： Xin Liu , Arvind Bomdica , Yikai Liang , Ming-Ju Edward Lee , Rohit Rathi , Jinyung Namkoong
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H03K19/018585
摘要： A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.
摘要翻译：双功能差分驱动器包括电压模式差分驱动器部分和电流模式差分驱动器部分。控制电路连接到电压模式差分驱动器部分和电流模式差分驱动器部分。控制电路将双功能差分驱动器作为电压模式差分驱动器操作，并作为电流模式差分驱动器进行操作。

5. 发明申请

US20110133788A1 DUAL FUNCTION VOLTAGE AND CURRENT MODE DIFFERENTIAL DRIVER 有权
标题翻译：双功能电压和电流模式差分驱动器
公开(公告)号：US20110133788A1
公开(公告)日：2011-06-09
申请号：US12633174
申请日：2009-12-08
申请人： Xin Liu , Arvind Bomdica , Yikai Liang , Ming-Ju Edward Lee , Rohit Rathi , Jinyung Namkoong
发明人： Xin Liu , Arvind Bomdica , Yikai Liang , Ming-Ju Edward Lee , Rohit Rathi , Jinyung Namkoong
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H03K19/018585
摘要： A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.
摘要翻译：双功能差分驱动器包括电压模式差分驱动器部分和电流模式差分驱动器部分。控制电路连接到电压模式差分驱动器部分和电流模式差分驱动器部分。控制电路将双功能差分驱动器作为电压模式差分驱动器操作，并作为电流模式差分驱动器进行操作。

6. 发明授权

US07522010B2 Ultra-low power crystal oscillator 有权
标题翻译：超低功耗晶体振荡器
公开(公告)号：US07522010B2
公开(公告)日：2009-04-21
申请号：US11797081
申请日：2007-04-30
申请人： Kevin YiKai Liang , Arvind Bomdica , Min Xu , Ming So
发明人： Kevin YiKai Liang , Arvind Bomdica , Min Xu , Ming So
IPC分类号： H03C1/00
CPC分类号： H03B5/364 , H03B2200/0082
摘要： An ultra-low power crystal oscillator architecture that draws less than 2 μA during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 μA.
摘要翻译：一种超低功耗晶体振荡器架构，在稳态运行期间吸收小于2μA。放大器级是自偏置的，并具有限制其信号摆幅的输入和输出钳位电路。选择电路值，使得第一放大器级有足够的瞬态负载电流进行振荡，同时输入和输出钳位电路保持级的足够低的摆幅，使得稳态平均负载电流在小于1亩。

7. 发明授权

US08570067B2 Method and apparatus for controlling a communication signal by monitoring one or more voltage sources 有权
标题翻译：通过监视一个或多个电压源来控制通信信号的方法和装置
公开(公告)号：US08570067B2
公开(公告)日：2013-10-29
申请号：US11749002
申请日：2007-05-15
申请人： Oleg Drapkin , Grigori Temkine , Marcus Ng , Kevin Yikai Liang , Arvind Bomdica , Siji Menokki Kandiyil , Ming So , Samu Suryanarayana
发明人： Oleg Drapkin , Grigori Temkine , Marcus Ng , Kevin Yikai Liang , Arvind Bomdica , Siji Menokki Kandiyil , Ming So , Samu Suryanarayana
IPC分类号： H03K19/0175
CPC分类号： H03K19/00384 , H03K17/223 , H04L25/028
摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.
摘要翻译：集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。可以使用功率斜坡传感器逻辑检测电压源上的电压。如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

8. 发明授权

US08102633B2 Power supply equalization circuit using distributed high-voltage and low-voltage shunt circuits 有权
标题翻译：电源均衡电路采用分布式高压和低压分流电路
公开(公告)号：US08102633B2
公开(公告)日：2012-01-24
申请号：US12406705
申请日：2009-03-18
申请人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
发明人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22
CPC分类号： H03K19/00315
摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.
摘要翻译：描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压或其他过大的电流条件的影响。每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。实施例的保护电路包括高电压IO引脚，降压网络，以将IO引脚上的高电压降低到浮置电压轨上的低电压电平;耦合在浮动电源轨和地之间的第一分流电路，耦合在浮动电源轨和低电压电源轨之间的均衡器电路，以及通过低压供电轨耦合到均衡器电路的第二分流电路。

9. 发明申请

US20110148838A1 BIAS CIRCUIT FOR A COMPLEMENTARY CURRENT MODE LOGIC DRIVE CIRCUIT 有权
标题翻译：用于补充电流模式逻辑驱动电路的偏置电路
公开(公告)号：US20110148838A1
公开(公告)日：2011-06-23
申请号：US12640180
申请日：2009-12-17
申请人： Kevin Yikai Liang , Xin Liu , Arvind Bomdica , Ming-Ju Edward Lee
发明人： Kevin Yikai Liang , Xin Liu , Arvind Bomdica , Ming-Ju Edward Lee
IPC分类号： G06F3/038 , G05F1/10
CPC分类号： H03K19/018514 , H03K19/018528
摘要： A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.
摘要翻译：电路包括互补电流模式逻辑驱动器电路和双反馈电流模式逻辑偏置电路。互补电流模式逻辑驱动器电路提供第一输出电压和第二输出电压。双反馈电流模式逻辑偏置电路包括第一反馈电路和第二反馈电路。第一反馈电路响应于第一输出电压为互补电流模式逻辑驱动器电路提供第一偏置电压。第二反馈电路响应于第二输出电压提供第二偏置电压。

10. 发明授权

US08432207B1 Method and apparatus for correcting the duty cycle of a high speed clock 失效
标题翻译：用于校正高速时钟的占空比的方法和装置
公开(公告)号：US08432207B1
公开(公告)日：2013-04-30
申请号：US13341017
申请日：2011-12-30
申请人： Jackie Chu , Yikai Liang
发明人： Jackie Chu , Yikai Liang
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： Methods and apparatuses are provided for duty cycle correction of high-speed clock circuits. The apparatus includes a duty cycle interpolator receiving a clock source for providing a duty cycle corrected clock signal. The duty cycle corrected clock signal is filtered and compared to a reference signal, the result of which is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to the duty cycle interpolator for adjusting the duty cycle of the clock signal to provide the duty cycle corrected clock signal. The method includes filtering a duty cycle corrected clock signal to provide a filtered signal and comparing the filtered signal to a reference signal, the result of is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to a duty cycle interpolator for adjusting the duty cycle of a clock signal.
摘要翻译：提供了用于高速时钟电路的占空比校正的方法和装置。该装置包括接收用于提供占空比校正时钟信号的时钟源的占空比内插器。对占空比校正时钟信号进行滤波并与参考信号进行比较，其参考信号被计时到一个移位寄存器中。移位寄存器向占空比内插器提供互补的N位占空比校正信号，用于调整时钟信号的占空比以提供占空比校正时钟信号。该方法包括对占空比校正的时钟信号进行滤波以提供经滤波的信号并将滤波的信号与参考信号进行比较，其结果被计时到移位寄存器中。移位寄存器向占空比内插器提供互补的N位占空比校正信号，用于调整时钟信号的占空比。

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