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1. 发明公开

CN105304512A 用于制造功率模块的方法以及功率模块无效
公开(公告)号：CN105304512A
公开(公告)日：2016-02-03
申请号：CN201510445932.1
申请日：2015-07-27
申请人：西门子公司
发明人：贝恩德·屈滕 , 米夏埃尔·莱佩纳特 , 龙尼·维尔纳
IPC分类号： H01L21/603
CPC分类号： H01L24/83 , H01L23/3735 , H01L24/27 , H01L24/29 , H01L24/32 , H01L2224/2745 , H01L2224/27452 , H01L2224/27462 , H01L2224/27464 , H01L2224/2908 , H01L2224/29082 , H01L2224/29111 , H01L2224/29147 , H01L2224/32225 , H01L2224/32503 , H01L2224/83201 , H01L2224/83203 , H01L2224/8381 , H01L2224/83825 , H01L2224/8383 , H01L2924/0002 , H01L2924/10155 , H01L2924/13055 , H01L2924/13091 , H01L2924/38 , H01L2924/386 , H01L2924/00 , H01L2224/26 , H01L2924/00012 , H01L2924/00014 , H01L24/80 , H01L2224/80 , H01L2224/83
摘要：本发明涉及一种用于制造功率模块(10)的方法。该方法包括提供具有上侧(14)和下侧(16)的第一构件(12)；将包括第一材料(36)的第一层(28)直接沉积到第一构件(12)的上侧(14)上；将包括与第一材料(36)不同的第二材料(38)的第二层(30)直接沉积到第一层(28)上；提供具有上侧(20)和下侧(22)的第二构件(18)，将第二构件(18)的下侧(22)布置在第二层(30)上并通过对第一构件(12)的下侧(16)和/或第二构件(18)的上侧(20)加载预定的力(FN1，FN2)使第一构件(12)和第二构件(18)材料配合地连接。

2. 发明公开

CN106129038A 集成电路芯片及其制作方法无效
公开(公告)号：CN106129038A
公开(公告)日：2016-11-16
申请号：CN201610552274.0
申请日：2016-07-14
申请人：成都芯源系统有限公司
发明人：肖明 , 姚泽强 , 李恒 , 银发友
IPC分类号： H01L23/522 , H01L23/528 , H01L21/768
CPC分类号： H01L23/49838 , H01L21/02271 , H01L21/31111 , H01L21/486 , H01L21/56 , H01L21/76871 , H01L23/3171 , H01L23/3192 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02381 , H01L2224/0239 , H01L2224/03462 , H01L2224/0347 , H01L2224/0391 , H01L2224/05096 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13082 , H01L2224/13111 , H01L2224/13611 , H01L2924/38 , H01L2924/014 , H01L2924/206 , H01L2924/00014 , H01L23/5226 , H01L21/76801 , H01L21/76886 , H01L23/528
摘要：本发明公开了一种包括再布线层和焊接凸起结构的集成电路芯片及其制作方法。所述集成电路芯片通过在再布线层的侧面或者侧面以及上表面覆盖绝缘介质层，从而避免了钝化层和塑封料之间的非紧密直接接触。本发明公开的集成电路芯片通过绝缘介质层与塑封料的紧密接触，避免了铜离子迁移通路的形成。

3. 发明公开

CN105845585A 一种芯片封装方法及芯片封装结构无效复审申请
公开(公告)号：CN105845585A
公开(公告)日：2016-08-10
申请号：CN201610292628.2
申请日：2016-04-28
申请人：合肥祖安投资合伙企业(有限合伙)
发明人：尤文胜
IPC分类号： H01L21/50 , H01L21/56 , H01L21/60 , H01L23/31 , H01L23/488
CPC分类号： H01L2224/16225 , H01L21/50 , H01L21/563 , H01L21/568 , H01L23/3107 , H01L24/12 , H01L24/81 , H01L2224/12 , H01L2224/81193 , H01L2924/37001 , H01L2924/38
摘要：本发明提供了一种芯片封装方法及芯片封装结构，先在封装载体上形成第一金属层，再在所述第一金属层上形成金属凸块，以及在金属凸块上上形成第一焊接层，然后将焊盘上直接电连接导电体的芯片以有源面朝向所述第一焊接层的方式，通过所述导电体电连接在第一焊接层上，最后经过塑封，使所述第一金属表面被塑封体裸露，以提供外部电连接。因此，所述芯片封装方法无需使用复杂的UBM工艺以及预成型的引线框架，提高了芯片封装的良率以及灵活性设计，且依据本发明提供的芯片封装结构具有较高的封装集成度和可靠性。

4. 发明申请

US20190067163A1 PARTIALLY MOLDED DIRECT CHIP ATTACH PACKAGE STRUCTURES FOR CONNECTIVITY MODULE SOLUTIONS 审中-公开
公开(公告)号：US20190067163A1
公开(公告)日：2019-02-28
申请号：US16102117
申请日：2018-08-13
申请人： Intel IP Corporation
发明人： Quan Qi , Carlton E. Hanna , Eytan Mann , Sidharth Dalmia
IPC分类号： H01L23/433 , H01L23/367 , H01L21/48 , H01L23/538 , H01L23/498 , H01L23/00
CPC分类号： H01L23/4334 , H01L21/4814 , H01L23/13 , H01L23/3128 , H01L23/3677 , H01L23/49816 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/96 , H01L2223/6677 , H01L2224/13101 , H01L2224/16225 , H01L2924/1432 , H01L2924/1434 , H01L2924/15153 , H01L2924/15311 , H01L2924/38 , H01L2924/014 , H01L2924/00014
摘要： Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

5. 发明授权

US09502327B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09502327B2
公开(公告)日：2016-11-22
申请号：US14913719
申请日：2015-01-09
申请人： DENSO CORPORATION
发明人： Shun Sugiura , Yasushi Ookura
IPC分类号： H01L23/367 , B23K3/08 , H01L23/00 , B23K1/00 , B23K1/008 , H01L23/433 , H01L23/495
CPC分类号： H01L23/3675 , B23K1/0016 , B23K1/008 , B23K3/087 , B23K2101/40 , H01L23/4334 , H01L23/49513 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/05554 , H01L2224/29101 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/83192 , H01L2224/83201 , H01L2224/83203 , H01L2224/83815 , H01L2224/83986 , H01L2224/85205 , H01L2224/92247 , H01L2924/00014 , H01L2924/13055 , H01L2924/181 , H01L2924/38 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/014
摘要： A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the first face of the semiconductor element; a second metal member disposed on a rear face of the semiconductor element; a first solder that connects the solder region of the semiconductor element and the first metal member; and a second solder that connects the rear face of the semiconductor element and the second metal member. At least the second solder provides a melt-bond. A gravity center position of the first metal member coincides with a center position of the semiconductor element in a projection view from a stacking direction.
摘要翻译：半导体器件包括：在第一面上具有焊料区域和非焊接区域的半导体元件; 设置在所述半导体元件的第一面上的第一金属构件; 设置在所述半导体元件的背面上的第二金属构件; 连接半导体元件的焊料区域和第一金属部件的第一焊料; 以及连接半导体元件的后表面和第二金属构件的第二焊料。至少第二焊料提供熔融粘合。第一金属构件的重心位置与半导体元件的从堆叠方向的投影视图的中心位置重合。

6. 发明授权

US09053405B1 Printed RFID circuit 有权
标题翻译：打印RFID电路
公开(公告)号：US09053405B1
公开(公告)日：2015-06-09
申请号：US14162483
申请日：2014-01-23
申请人： Flextronics AP, LLC
发明人： Weifeng Liu , Anwar Mohammed , Murad Kurwa
IPC分类号： G06K19/07 , G06K19/077 , H01M6/40
CPC分类号： H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要： A printed circuit including a non-conductive substrate, a first conductive layer printed on the non-conductive substrate and one or more additional layers printed on the substrate. The first conductive layer is able to have one or more antennas each forming a predetermined pattern, a first conductive sheet and one or more conductive traces. The one or more additional layers include a first electrode printed on the top of the first conductive sheet, a buffer printed on top of the first electrode, a second electrode printed on top of the buffer and a second conductive sheet printed on top of the second electrode. The printed circuit is further able to include an RFID chip electrically coupled with the antennas and at least one of the first and second conductive sheets via the conductive traces, wherein the first and second conductive sheets, the buffer and the first and second electrodes form a power source that provides electrical power to the RFID chip.
摘要翻译：一种印刷电路，包括非导电衬底，印刷在非导电衬底上的第一导电层和印刷在衬底上的一个或多个附加层。第一导电层能够具有各自形成预定图案的一个或多个天线，第一导电片和一个或多个导电迹线。所述一个或多个附加层包括印刷在第一导电片的顶部上的第一电极，印刷在第一电极顶部上的缓冲器，印刷在缓冲器顶部的第二电极和印刷在第二导电片的第二个顶部上的第二导电片电极。印刷电路还能够包括通过导电迹线与天线以及第一和第二导电片中的至少一个电耦合的RFID芯片，其中第一和第二导电片，缓冲器和第一和第二电极形成向RFID芯片提供电力的电源。

7. 发明公开

US20230170322A1 GANG CLIP WITH MOUNT COMPOUND ARRESTER 审中-公开
公开(公告)号：US20230170322A1
公开(公告)日：2023-06-01
申请号：US17536498
申请日：2021-11-29
申请人： Texas Instruments Incorporated
发明人： Ernesto Pentecostes Rafael, JR. , Kristina Dianne Hernandez Sazon , Dior Yñigo Medina Gadia
IPC分类号： H01L23/00 , H01L25/065 , H01L23/495
CPC分类号： H01L24/37 , H01L24/32 , H01L24/38 , H01L25/0657 , H01L23/49575 , H01L2224/32245 , H01L2224/3702 , H01L2924/38
摘要： An integrated circuit package includes a lead frame, a first die adhered to the lead frame on a first side of the first die, and a first clip having a clip foot adhered to the lead frame. The first clip has a first side and a second side. A first die attachment region is defined by a first group of four notches in the first side of the first clip. The first clip extends from the lead frame and contacts a second side of the first die at the first die attachment region via a first layer of solder paste. The integrated circuit package further has a second die adhered to the second side of the first clip on a first side of the second die, and a second clip having a clip foot adhered to the lead frame. The second clip has a first side and a second side. A second die attachment region is defined by a second group of four notches in the first side of the second clip. The second clip extends from the lead frame and contacts a second side of the second die at the second die attachment region via a second layer of solder paste.

8. 发明授权

US09661756B1 Nano-copper pillar interconnects and methods thereof 有权
公开(公告)号：US09661756B1
公开(公告)日：2017-05-23
申请号：US14455642
申请日：2014-08-08
申请人： Flextronics AP, LLC
发明人： Jennifer Nguyen , David Geiger , Anwar Mohammed , Murad Kurwa
IPC分类号： H05K1/09 , H05K3/24 , H05K1/11 , H05K3/30 , H05K3/40
CPC分类号： H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要： Embodiments of the present invention relate to nano-copper pillar interconnects. Nano-copper material is a mixture of nano-copper particles and one or more organic fluxes. In some embodiments, the one or more organic fluxes include organic solvents that help bind the nano-copper particles together and allow the nano-copper material to be printable. The nano-copper material is applied onto bond pads on a printed circuit board (PCB) via a printing process, a dipping process or the like, to form nano-copper covered PCB bond pads. A component can thereafter be coupled with the PCB at the nano-copper covered PCB bond pads. What is left when the solvents evaporate are nano-copper pillar interconnects that form, coupling the component with the PCB bond pads. The nano-copper pillar interconnects are of pure copper.

9. 发明授权

US09397065B1 Fixture design for pre-attachment package on package component assembly 有权
标题翻译：夹具组件装配前套件的夹具设计
公开(公告)号：US09397065B1
公开(公告)日：2016-07-19
申请号：US14468216
申请日：2014-08-25
申请人： Flextronics AP, LLC
发明人： Jennifer Nguyen , David Geiger , Ranilo Aranda , Jonas Sjoberg , Anwar Mohammed , Murad Kurwa
IPC分类号： H01L23/544 , H01L23/00 , H01L25/00 , H01L23/538
CPC分类号： H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要： Embodiments of the present invention relate to a fixture design for pre-attachment package on package component assembly. The fixture design includes a plurality of pockets arranged in a N×M array. The plurality of pockets is sized to receive bottom packages. The fixture design includes global fiducials that are used to locate positions of the pockets on the fixture, and sets of local fiducials, with each set being specific to one of the pockets and used to refine the position of the location of a corresponding pocket. Each of the pockets can include one or more ear cuts for easy component placement and component removal. The fixture design can include a vacuum port for coupling with a vacuum source for drawing a vacuum to hold the bottom packages down. The fixture design can also include a cover that is used with the fixture to keep the components from being disturbed.
摘要翻译：本发明的实施例涉及一种用于包装部件组件上的预附接包装的夹具设计。夹具设计包括以N×M阵列排列的多个口袋。多个口袋的尺寸适于接纳底部包装。夹具设计包括用于定位夹具上的凹穴的位置的全局基准和局部基准的集合，其中每一组特定于其中一个凹穴并且用于细化相应凹穴的位置的位置。每个口袋可以包括一个或多个耳朵切口，便于元件放置和元件移除。夹具设计可以包括用于与真空源耦合的真空端口，用于抽真空以将底部包装件向下保持。夹具设计还可以包括与夹具一起使用以防止部件受到干扰的盖子。

10. 发明申请

WO2015107879A1 半導体装置及びその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2015107879A1
公开(公告)日：2015-07-23
申请号：PCT/JP2015/000072
申请日：2015-01-09
申请人：株式会社デンソー
发明人：杉浦　俊 , 大倉　康嗣
IPC分类号： H01L23/36 , B23K1/00 , H01L23/40
CPC分类号： H01L23/3675 , B23K1/0016 , B23K1/008 , B23K3/087 , B23K2201/40 , H01L23/4334 , H01L23/49513 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/05554 , H01L2224/29101 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/83192 , H01L2224/83201 , H01L2224/83203 , H01L2224/83815 , H01L2224/83986 , H01L2224/85205 , H01L2224/92247 , H01L2924/00014 , H01L2924/13055 , H01L2924/181 , H01L2924/38 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/014
摘要：　半導体装置は、一面にはんだ領域（１２ａ１）と非はんだ領域（１２ａ２）を有する半導体素子（１２）と、前記半導体素子の一面側に配置される第１金属部材（２２）と、前記半導体素子の裏面側に配置される第２金属部材（１８）と、前記半導体素子の前記はんだ領域と前記第１金属部材とを接続する第１はんだ（２０）と、前記半導体素子の前記裏面と前記第２金属部材とを接続する第２はんだ（１６）とを備える。少なくとも第２はんだは溶融接合を提供する。前記積層の方向からの投影視において、前記第１金属部材の重心位置（Ｃｇ）が、前記半導体素子の中心位置（Ｃ１）と一致している。
摘要翻译：该半导体装置设置有：在一个表面上包括焊料区域（12a1）和非焊接区域（12a2）的半导体元件（12）布置在所述半导体元件的一个表面侧上的第一金属构件（22）; 布置在半导体元件的背面侧的第二金属构件（18）连接半导体元件的焊料区域和第一金属部件的第一焊料（20）; 以及将半导体元件的背面和第二金属构件相互连接的第二焊料（16）。至少第二焊料提供熔融粘合。在从层叠方向的投影视图中，第一金属构件的重心位置（Cg）与半导体元件的中心（C1）的位置一致。

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