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1. 发明授权

EP2836058B1 VERTICAL ORTHOGONAL INTERCONNECTION SYSTEM AND COMMUNICATION DEVICE 有权
标题翻译：垂直正交连接系统和通信设备
公开(公告)号：EP2836058B1
公开(公告)日：2016-12-07
申请号：EP12876061.8
申请日：2012-10-26
申请人： Huawei Technologies Co., Ltd.
发明人： WANG, Baoqi , ZHANG, Guodong , LIU, Fangming
IPC分类号： H05K7/02 , H01R12/00 , H04Q1/02
CPC分类号： H01R12/737 , H04Q1/15 , H05K1/14 , H05K3/366 , H05K5/0065 , H05K7/1445 , H05K2201/044 , H05K2201/10189
摘要： The present invention is applicable to the field of communications technologies, and provides a perpendicular and orthogonal interconnection system and a communications device. The perpendicular and orthogonal interconnection system includes a first board group, a second board group orthogonal to the first board group, and a center backplane arranged between the first board group and the second board group, where the first board group includes a plurality of first boards parallel to each other, and the second board group includes a plurality of second boards parallel to each other; a plurality of curved male connectors is arranged on each of the first boards, a plurality of curved female connectors is arranged on each of the second boards, and the curved male connectors and the curved female connectors directly cooperate and are connected in one-to-one correspondence. In the present invention, the curved male connectors and the curved female connectors directly cooperate and are connected. When the perpendicular and orthogonal interconnection system is upgraded, only the board that permanently has the curved male connectors and the curved female connectors needs to be replaced, which is rather simple and shortens a signal link. Based on the foregoing advantages, the perpendicular and orthogonal interconnection system is applicable to various communications devices; therefore, its upgrade is convenient, signal quality is improved, heat dissipation is ideal, and material costs are saved.

2. 发明公开

EP2996446A1 High speed routing module 审中-公开
标题翻译： Hochgeschwindigkeitsroutingmodul
公开(公告)号：EP2996446A1
公开(公告)日：2016-03-16
申请号：EP14290297.2
申请日：2014-09-12
申请人： ALCATEL LUCENT
发明人： Brachmann, Markus , Goetz, Hans-Joachim , Keck, Michael
IPC分类号： H05K1/02 , H05K1/14
CPC分类号： H05K1/0243 , H05K1/114 , H05K1/141 , H05K2201/044 , H05K2201/09227 , H05K2201/10734
摘要： A printed circuit board, PCB, device (10) comprises:
- a first PCB module (4),
- a second PCB module (11), and
- at least two electrical components (2, 5) mounted on the first PCB module (4), wherein a signal from a first one of the electrical components (2) to a second one of the electrical components (5) is routed via the second PCB module (11).
摘要翻译：印刷电路板，PCB，器件（10）包括： - 第一PCB模块（4）， - 第二PCB模块（11），以及 - 安装在所述第一PCB模块上的至少两个电气部件（2,5） 4），其中来自所述电气部件（2）中的第一个到所述电气部件（5）中的第二个的信号经由所述第二PCB模块（11）布线。

3. 发明授权

EP2723027B1 Three-dimensional backplane 有权
标题翻译：三维背板
公开(公告)号：EP2723027B1
公开(公告)日：2015-12-30
申请号：EP13181965.8
申请日：2013-08-28
申请人： Huawei Technologies Co., Ltd.
发明人： Chen, Songhai , Tang, Shiping
IPC分类号： H04L12/931 , H04L12/933 , H05K1/11
CPC分类号： H05K3/366 , H04L49/40 , H05K2201/044

4. 发明公开

EP2945470A1 ELECTRONIC DEVICE, ELECTRONIC SYSTEM AND CIRCUIT BOARD INTERCONNECTION ARCHITECTURE THEREOF 审中-公开
标题翻译： ELEKTRONISCHE VORRICHTUNG，ELEKTRONISCHES SYSTEM UND LEITERPLATTENVERBINDUNGSARCHITEKTURDAFÜR
公开(公告)号：EP2945470A1
公开(公告)日：2015-11-18
申请号：EP13874793.6
申请日：2013-08-07
申请人： Huawei Technologies Co., Ltd.
发明人： BAI, Lei , LIU, Xiongbiao , PENG, Lexiong
IPC分类号： H05K1/11
CPC分类号： H05K3/366 , H01R12/722 , H01R12/737 , H05K1/117 , H05K1/14 , H05K2201/044 , H05K2201/09063 , H05K2201/09163 , H05K2201/10189
摘要： The present invention discloses a circuit board interconnection architecture, which includes at least one first plugboard and at least two second plugboards substantially perpendicular to the first plugboard, where at least one of the first plugboard and the second plugboards is provided with several slots; the first plugboard and the second plugboards are mated and electrically connected by using signal connectors on both sides of the slots. The circuit board interconnection architecture solves a fitting precision problem of the first plugboard and the second plugboards in orthogonal directions. Even though there is an assembly tolerance between the first plugboard and the second plugboards, the connectors still satisfy assembly precision requirements, which can also avoid overall deformation of a first circuit board and a second circuit board after the first plugboard and the second plugboards are interconnected and mated orthogonally. The present invention further provides an electronic system and an electronic device which uses the electronic system.
摘要翻译：本发明公开了一种电路板互连架构，其包括至少一个第一插板和至少两个基本上垂直于第一插板的第二插板，其中第一插板和第二插板中的至少一个设置有多个插槽; 第一插板和第二插板通过在插槽的两侧使用信号连接器来配合和电连接。电路板互连架构解决了第一插板和第二插板在正交方向上的拟合精度问题。即使在第一插板和第二插板之间存在组装公差，连接器仍然满足组装精度要求，这也可以避免在第一插板和第二插板相互连接之后第一电路板和第二电路板的整体变形并正交配对。本发明还提供一种使用电子系统的电子系统和电子设备。

5. 发明授权

EP1831971B1 DIFFERENTIAL ELECTRICAL CONNECTOR ASSEMBLY 有权
标题翻译：差分电连接器组件
公开(公告)号：EP1831971B1
公开(公告)日：2015-11-18
申请号：EP05855660.6
申请日：2005-12-23
申请人： AMPHENOL CORPORATION
发明人： COHEN, Thomas S. , GAILUS, Mark W. , DUNHAM, John R.
IPC分类号： H01R12/71 , H01R12/72 , H01R13/64 , H05K1/14 , H05K7/14 , H01R4/66 , H01R12/58 , H01R13/658 , H01R13/514
CPC分类号： H01R12/716 , H01R12/585 , H01R12/724 , H01R12/727 , H01R13/514 , H01R13/6474 , H01R13/6587 , H01R13/6591 , H05K1/14 , H05K7/1445 , H05K2201/044 , H05K2201/10189 , H05K2203/1572

6. 发明公开

EP2822372A1 Gehäuse zur Aufnahme von elektronischen Steckkarten 有权
标题翻译： Gehäusezur Aufnahme von elektronischen Steckkarten
公开(公告)号：EP2822372A1
公开(公告)日：2015-01-07
申请号：EP13175312.1
申请日：2013-07-05
申请人： Pentair Technical Solutions GmbH
发明人： Dizel, Sergej , Mann, Dietmar , Gauges, Dietmar , Müller, Jochen
IPC分类号： H05K7/14 , H05K1/14
CPC分类号： H05K5/0256 , H05K1/144 , H05K7/1427 , H05K7/1445 , H05K2201/042 , H05K2201/044 , H05K2201/09036 , H05K2201/10409 , H05K2201/2036 , Y10T29/53183
摘要： Ein Gehäuse (1) zur Aufnahme von elektronischen Steckkarten (4a) umfasst eine Front (2), eine Rückseite (3), einen vorderen Kartenkorb (5) zum Einbau von Steckkarten (4a) von der Front (2) her, einen hinteren Kartenkorb (6) zum Einbau von Steckkarten (4a) von der Rückseite (3) her, eine erste vertikale Backplane (7), die am Ende des vorderen Kartenkorbs (5) so befestigt ist, dass ihre Vorderseite (8) zur Front (2) des Gehäuses (1) weist, ferner eine zweite vertikale Backplane (11) parallel und mit Abstand auf der Rückseite (9) der ersten Backplane (7) so angeordnet ist, dass die Vorderseite (12) der zweiten Backplane (11) zur Rückseite (3) des Gehäuses (1) weist. Abstandshalter (14) verbinden die beiden Backplanes (7, 11) miteinander.
An mindestens einer der einander zugewandten Rückseiten (9, 13) der beiden parallelen Backplanes (7, 11) sind Plansenkungen vorgesehen, auf deren Grund die Abstandshalter (14) anliegen. Die Tiefen der Plansenkungen sind derart gewählt, dass der Abstand (s 1 ) zwischen der Vorderseite (12) der zweiten Backplane (11) und der Front (2) des Gehäuses (1) einem vorbestimmten Wert entspricht. Dadurch ist sichergestellt, dass der hintere Kartenkorb (6) ausreichend tief ist, unabhängig von der schwankenden Dicke der Backplanes (7, 11).
摘要翻译：用于容纳电子插件卡的机柜具有用于插入插卡和第一和第二垂直背板的前后卡筐。第一背板的前侧面向机柜的前部，第二个背板的前侧面向机柜后部。距离件连接两个底板，并且在两个背板的至少一个后侧设置沉孔。钻孔后沉孔的深度或底板的残余厚度的尺寸使得第二背板的前侧与机柜前部之间的距离是预定值。这样可确保推到第二背板上的插卡完全接收在后卡筐内，插卡的前板与后卡筐齐平。

7. 发明授权

EP1831970B1 MIDPLANE ESPECIALLY APPLICABLE TO AN ORTHOGONAL ARCHITECTURE ELECTRONIC SYSTEM 有权
标题翻译：特别是对于电子ORTHOGONALARCHITEKTURSYSTEM适用平面
公开(公告)号：EP1831970B1
公开(公告)日：2014-04-09
申请号：EP05855654.9
申请日：2005-12-23
申请人： AMPHENOL CORPORATION
发明人： COHEN, Thomas, S. , CARTIER, JR., Marc B. , GAILUS, Mark W.
IPC分类号： H01R13/648
CPC分类号： H05K7/1445 , H01R13/514 , H01R13/6587 , H01R13/6591 , H05K1/0231 , H05K1/0237 , H05K1/116 , H05K1/14 , H05K3/429 , H05K2201/044 , H05K2201/09236 , H05K2201/09718 , H05K2201/10189 , H05K2203/1572

8. 发明公开

EP2528421A1 Serial link interconnection arrangement for backplane with embedded waveguide 有权
标题翻译：与背板具有嵌入波导串行连接的连接装置
公开(公告)号：EP2528421A1
公开(公告)日：2012-11-28
申请号：EP11305644.4
申请日：2011-05-26
申请人： Alcatel Lucent
发明人： Hooghe, Koen
IPC分类号： H05K1/14
CPC分类号： H05K1/14 , H01P5/103 , H05K1/0243 , H05K1/141 , H05K7/1459 , H05K2201/0311 , H05K2201/044 , H05K2201/10189
摘要： A serial link interconnection arrangement for interconnecting a first printed circuit board (BoardA) with a second printed circuit board (BoardB), both boards being inserted in a backplane of a telecommunication system. The arrangement comprises a waveguide embedded in the backplane. A first end (WavA) of the waveguide is coupled to the first board (BoardA) via a first connection system (ConA), whilst the second end (WavB) of the waveguide is coupled to the second board (BoardB) via a second connection system (ConB). Each of the connection systems (ConA; ConB) comprises a transceiver (IntA; IntB) adapted to convert a parallel signal received from the printed circuit board (BoardA; BoardB) into a serial stream transmitted to an end (WavA; WavB) of the waveguide via an antenna (AntA; AntB), and vice-versa.
摘要翻译：用于第一印刷电路板（BoardA）与第二印刷电路板（BoardB）两种板被插入电信系统的背板上。互连串行链路互连装置，该装置包括嵌入在所述背板的波导。波导的第一端（WAVA）经由第一连接系统（Con A的）耦合到所述第一板（BoardA），而第二端（WavB）的波导通过第二连接耦合到所述第二板（BoardB）系统（CONB）。各连接系统（刀豆; CONB）包括收发器（INTA; INTB）angepasst转换为并行信号从印刷电路板接收（BoardA; BoardB）插入mitted到结束的串行流反式;的（WAVA WavB）经由天线波导（安塔; ANTB），并且反之亦然。

9. 发明公开

EP2419971A1 METHOD AND SYSTEM FOR REDUCING TRACE LENGTH AND CAPACITANCE IN A LARGE MEMORY FOOTPRINT BACKGROUND 审中-公开
标题翻译：方法和系统用于减少迹长和能力大有来头MEMORY根据地
公开(公告)号：EP2419971A1
公开(公告)日：2012-02-22
申请号：EP09843464.0
申请日：2009-04-17
申请人： Hewlett-Packard Company
发明人： KADRI, Rachid, M. , CONTRERAS, Stephen F.
IPC分类号： H01R12/16 , H01R12/18 , H01R12/36
CPC分类号： H05K1/181 , G11C5/066 , H05K1/0237 , H05K1/114 , H05K1/14 , H05K2201/044 , H05K2201/09227 , H05K2201/10189 , H05K2201/10545 , Y02P70/611 , Y10T29/49147
摘要： A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

10. 发明公开

EP1884953A3 High frequency bus system 审中-公开
标题翻译： RF总线系统
公开(公告)号：EP1884953A3
公开(公告)日：2008-04-02
申请号：EP07114348.1
申请日：1998-09-22
申请人： Rambus, Inc.
发明人： Perino, Donald, V. , Garrett, Billy, Wayne, Jr. , Liaw, Haw-Jyh , Nguyen, David , Nimmagadda, Srinivas , Gasbarro, James, A. , Dewitt Crisp, Richard
IPC分类号： G11C5/00 , G11C5/06
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , G11C7/1048 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/14 , H05K7/1459 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system (450) which insures uniform arrival times of high fidelity signals to the devices (510), despite the use of the bus (450) on modules (420) and connectors. The high frequency bus system (450) includes a first bus segment having one or more devices (510) connected between a first and second end. The high frequency bus system (450) also includes a second bus segment which has no devices connected to it. The first end of the first segment and the second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at substantially the same time, they arrive at each device (510) connected to the first bus segment at substantially the same time. Conversely when two signals originate at a device (510) substantially at the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data, or control, carried by the signals.

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