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1. 发明专利

JP2010124327A Phase detection circuit and phase detection method 审中-公开
标题翻译：相位检测电路和相位检测方法
公开(公告)号：JP2010124327A
公开(公告)日：2010-06-03
申请号：JP2008297085
申请日：2008-11-20
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： MATSUI TAKEO
IPC分类号： H04N5/06 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To simplify a device configuration in the case of digitizing a phase error according to a wide range frequency of a pixel clock signal. SOLUTION: A phase detection circuit 1 in which a unit delay time is made variable includes: a delay time calculation section 11 for calculating the time difference of two signal changes as enumerated values which are integral multiples of the unit delay time; a delay amount adjustment circuit 12; and a drive circuit 13. The delay time calculation section 11 performs calculation and an output in time sharing, respectively, considering predetermined times of a cycle of pixel clock signal CLK as enumerated data N1 (N1 is a positive integer) and considering the time difference between an edge of a horizontal synchronizing signal HS and an edge of a pixel clock signal CLK immediately before the edge as enumerated data N2 (N2 is a positive integer). The delay amount adjustment circuit 12 adjusts the unit delay time based on the enumerated data N1. The drive circuit 13 calculates N2/N1 as phase information between the horizontal synchronizing signal HS and the pixel clock signal CLK and outputs it. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了简化根据像素时钟信号的宽范围频率对相位误差进行数字化的情况下的器件配置。解决方案：其中单位延迟时间可变的相位检测电路1包括：延迟时间计算部分11，用于计算作为单位延迟时间的整数倍的枚举值的两个信号改变的时间差; 延迟量调节电路12; 延迟时间计算部分11分别考虑了作为列举数据N1（N1为正整数）的像素时钟信号CLK的周期的预定时间的时间共享的计算和输出，并考虑时间差在水平同步信号HS的边缘和刚好在边缘之前的像素时钟信号CLK的边缘作为枚举数据N2（N2是正整数）。延迟量调整电路12基于枚举数据N1调整单位延迟时间。驱动电路13计算N2 / N1作为水平同步信号HS和像素时钟信号CLK之间的相位信息，并输出。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010123798A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010123798A
公开(公告)日：2010-06-03
申请号：JP2008297030
申请日：2008-11-20
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： KANEKO ATSUSHI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To reduce an on-state resistance, and improve an avalanche resistance.
SOLUTION: In a method of manufacturing a semiconductor device according to the present embodiment, a buried gate electrode is formed in a pair of trenches in a substrate in such a manner as to be embedded in the position lower than the upper end of the trenches. A base region is formed in a predetermined region that is sandwiched between a pair of the trenches, and a source region is formed at the upper part of the base region.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：降低导通电阻，并提高雪崩电阻。解决方案：在根据本实施例的半导体器件的制造方法中，掩埋栅极形成在衬底中的一对沟槽中，以便嵌入在比上述壕沟基部区域形成在夹在一对沟槽之间的预定区域中，并且源极区域形成在基极区域的上部。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2010123781A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010123781A
公开(公告)日：2010-06-03
申请号：JP2008296567
申请日：2008-11-20
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： SASA KENJI
IPC分类号： H01L21/027 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To keep the dimension of a resist opening to be within an allowable range and to reduce the variations of the dimension of resist opening.
SOLUTION: The method of manufacturing a semiconductor device includes the steps of: forming a base film on the semiconductor substrate; forming a resist film having a predetermined opening thereon; and processing the base film while using the resist film as a mask. The method is used to determine the film thickness of the resist film in consideration of the film thickness of the base film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了保持抗蚀剂开口的尺寸在允许范围内，并且减小抗蚀剂开口尺寸的变化。解决方案：半导体器件的制造方法包括以下步骤：在半导体衬底上形成基膜; 在其上形成具有预定开口的抗蚀剂膜; 并且在使用抗蚀剂膜作为掩模的同时处理基膜。考虑到基膜的膜厚度，该方法用于确定抗蚀剂膜的膜厚度。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2010123669A Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010123669A
公开(公告)日：2010-06-03
申请号：JP2008294520
申请日：2008-11-18
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： TSUTSUI HAJIME
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823462 , H01L21/82345
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which either of an FET having a low threshold voltage and an FET having a high threshold voltage has characteristics of high performance.
SOLUTION: The semiconductor device 100 has the FET 102 and the FET 104, having the higher threshold voltage than the FET 102, on the same semiconductor substrate. The FET 102 has a gate insulating film 114 and a gate electrode 126. The FET 104 has a gate insulating film 114 and a gate electrode 121. The gate electrode 126 of the FET 102 and the gate insulating film 114 and gate electrode 121 of the FET 104 include at least one metal selected from a group of Hf, Zr, Al, La, Pr, Y, Ta, and W. The metal is higher in concentration on an interface between the gate insulating film 114 and gate electrode 121 of the FET 104 than on an interface between the gate insulating film 114 and gate electrode 126 of the FET 102.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：为了提供一种半导体器件，其中具有低阈值电压的FET或具有高阈值电压的FET中的任一个具有高性能的特性。解决方案：在相同的半导体衬底上，半导体器件100具有比FET 102高的阈值电压的FET 102和FET 104。 FET102具有栅极绝缘膜114和栅电极126.FET 104具有栅极绝缘膜114和栅电极121.FET 102的栅极126和栅极绝缘膜114以及栅极电极121 FET 104包括选自Hf，Zr，Al，La，Pr，Y，Ta和W中的至少一种金属。金属在栅绝缘膜114和栅极电极121之间的界面上的浓度较高 FET 104比在FET 102的栅极绝缘膜114和栅电极126之间的界面上更高。（C）2010，JPO＆INPIT

5. 发明专利

JP2010122946A Model parameter extractor and model parameter extraction program for semiconductor device model 有权
标题翻译：模型参数提取器和半导体器件模型的模型参数提取程序
公开(公告)号：JP2010122946A
公开(公告)日：2010-06-03
申请号：JP2008296576
申请日：2008-11-20
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： HATANAKA YUKICHI
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5036
摘要： PROBLEM TO BE SOLVED: To perform model parameter extraction so as to eliminate characteristic deflection of a model. SOLUTION: A model parameter extractor (1) includes: a binning processing unit (18) for performing binning processing; and a model parameter extraction unit (11) for extracting a model parameter for each of multiple bins formed through binning processing. The model parameter extraction unit (11) extracts a first model parameter (P2A) corresponding to a first end (A) of a target bin. A candidate (P2B') for a second model parameter (P2B) corresponding to a second end (B) of the target bin is set based on the first model parameter (P2A). A start-point-side gradient and an end-point-side gradient of a finite curve representing an electrical characteristic of a semiconductor device are specified based on the first model parameter (P2A) and the candidate (P2B') for the second model parameter. Then, the second model parameter (P2B) is extracted based on a result of comparison between the gradients. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：执行模型参数提取，以消除模型的特征偏移。模型参数提取器（1）包括：分级处理单元（18），用于执行合并处理; 以及模型参数提取单元（11），用于提取通过装箱处理形成的多个箱中的每一个的模型参数。模型参数提取单元（11）提取与目标仓的第一端（A）对应的第一模型参数（P2A）。基于第一模型参数（P2A）来设置与目标仓的第二端（B）对应的第二模型参数（P2B）的候选（P2B'）。基于第一模型参数（P2A）和第二模型参数的候选（P2B'）来指定表示半导体器件的电特性的有限曲线的起点侧梯度和终点侧梯度。然后，基于梯度之间的比较结果提取第二模型参数（P2B）。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2010122438A Method, program and device for verifying lithographic simulation model 审中-公开
标题翻译：用于验证光刻模拟模型的方法，程序和设备
公开(公告)号：JP2010122438A
公开(公告)日：2010-06-03
申请号：JP2008295659
申请日：2008-11-19
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： KATO YOSHIHIRO
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01L21/027 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To provide a technology for appropriately verifying the accuracy of a simulation model of a semiconductor layout pattern. SOLUTION: A plurality of simulation patterns is generated by executing simulation using a plurality of lithographic simulation models based on design data of a pattern of semiconductor device. Two or more designation areas and different weights for the respective designation areas are designated to the pattern of semiconductor device. With respect to each of the plurality of simulation patterns, a weighted average value of slippage from an actual pattern of semiconductor device is calculated. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于适当地验证半导体布局图案的仿真模型的精度的技术。解决方案：通过使用基于半导体器件的图案的设计数据的多个光刻仿真模型执行仿真来生成多个仿真模式。对于各个指定区域的两个或多个指定区域和不同的权重被指定为半导体器件的图案。对于多个模拟图案中的每一个，计算来自半导体装置的实际图案的滑移的加权平均值。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010119166A Voltage conversion circuit and semiconductor device 审中-公开
标题翻译：电压转换电路和半导体器件
公开(公告)号：JP2010119166A
公开(公告)日：2010-05-27
申请号：JP2008288845
申请日：2008-11-11
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： IGARASHI HATSUHIDE
IPC分类号： H02M3/155 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To secure the safety when operated with a lower power voltage.
SOLUTION: A voltage conversion circuit includes: NMOS transistors NM1 and NM2, which repeat ON-OFF operation for boosting the voltage of a power supply Vbat; a driving circuit 11, which switches on or switches off NM1; a driving circuit 12, which switches on or switches off NM2; and a comparator CMP2, which smoothes the boosted voltage and detects whether the smoothed voltage has surpassed a specified value. After power ON, it activates the driving circuit 11, and in case that the comparator CMP2 detects the smoothed voltage having surpassed the specified value, it non-activates the driving circuit 11 and activates the driving circuit 12. NM1 is so structured as to lower its threshold voltage than NM2, and its source is grounded, and its gate is supplied with an ON-OFF drive signal from the driving circuit 11. It includes an NMOS transistor NM3, in which the source is connected to the drain of NM1, and the gate is supplied with power Vbat, and the drain is connected to the drain (node P) of NM2.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了在以较低的电源电压工作时确保安全性。解决方案：电压转换电路包括：NMOS晶体管NM1和NM2，其重复ON-OFF操作，用于升压电源Vbat的电压; 驱动电路11，其接通或断开NM1; 驱动电路12，其接通或断开NM2; 以及比较器CMP2，其平滑升压电压并检测平滑电压是否超过规定值。电源接通后，激活驱动电路11，在比较器CMP2检测出超过规定值的平滑电压的情况下，不激活驱动电路11并使驱动电路12启动.NM1的结构如下其门限电压高于NM2，其源极接地，其栅极由驱动电路11提供ON-OFF驱动信号。它包括NMOS晶体管NM3，源极连接到NM1的漏极，以及栅极被供给电压Vbat，漏极连接到NM2的漏极（节点P）。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2010118893A Device, method, and program for generating packet 审中-公开
标题翻译：用于生成分组的设备，方法和程序
公开(公告)号：JP2010118893A
公开(公告)日：2010-05-27
申请号：JP2008290687
申请日：2008-11-13
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： TAZAKI TOSHIO
IPC分类号： H04L1/00
摘要： PROBLEM TO BE SOLVED: To reduce overhead in data transmission using packets consisting of at least one data unit. SOLUTION: A packet generation device 100 generates packets consisting of a data unit including transmission data and information for error detection. The packet generation device includes: an error occurrence situation monitor 1 for monitoring an error occurrence situation in data units by transmission results returned from a reception side for a transmitted packet; a packet size calculation unit 2 for calculating an error occurrence probability by the error occurrence situation, and calculating correction data length, where the data length of the last packet has been corrected, based on a correlation among the error occurrence probability, the data length of packets, and overhead; and a packet generation unit 3 for generating a packet comprising at least one data unit by data to be transmitted and correction data length. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使用由至少一个数据单元组成的分组来减少数据传输的开销。解决方案：分组生成设备100生成包括由包括传输数据的数据单元和用于错误检测的信息组成的分组。分组生成装置包括：错误发生状况监视器1，用于通过从发送分组的接收侧返回的发送结果监视数据单元中的错误发生情况; 分组大小计算单元2，用于通过错误发生情况计算错误发生概率，并且基于错误发生概率之间的相关性来计算最后分组的数据长度已经被校正的校正数据长度，数据包和开销; 以及分组生成单元3，用于通过要发送的数据和校正数据长度来生成包括至少一个数据单元的分组。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2010118748A Semiconductor integrated circuit device and control method of delay line 有权
标题翻译：半导体集成电路设备及延时线控制方法
公开(公告)号：JP2010118748A
公开(公告)日：2010-05-27
申请号：JP2008288846
申请日：2008-11-11
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： NOMURA MASAHIRO
IPC分类号： H03K5/00 , H01L21/822 , H01L27/04 , H03K5/26 , H03K19/0175
CPC分类号： H03K5/135 , H03K5/26
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of improving power efficiency. SOLUTION: The semiconductor integrated circuit device includes two synchronous operation circuits 11 and 12, a plurality of delay lines 13a, 13b, ..., 13n, a delay detection unit 14, and a control unit 15. The two synchronous operation circuits operate by synchronizing with a clock signal CLK. The plurality of delay lines 13a, 13b, ..., 13n are connected between the two synchronous operation circuits in a parallel configuration to enable signal transmission. The delay detection unit detects each delay time in the plurality of delay lines 13a, 13b, ..., 13n. The control unit controls to select one delay line among the plurality of delay lines based on the detection result by the delay detection unit 14, and prevent signal transmissions other than the one delay line selected. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够提高功率效率的半导体集成电路器件。解决方案：半导体集成电路器件包括两个同步操作电路11和12，多个延迟线13a，13b，...，13n，延迟检测单元14和控制单元15.两个同步操作电路通过与时钟信号CLK同步来工作。多个延迟线13a，13b，...，13n以并联配置连接在两个同步运算电路之间，以使信号传输。延迟检测单元检测多个延迟线13a，13b，...，13n中的每个延迟时间。控制单元基于延迟检测单元14的检测结果，控制多个延迟线中的一个延迟线，并且防止选择的一个延迟线以外的信号传输。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2010118718A Data processing apparatus and processing method therefor 审中-公开
标题翻译：数据处理装置及其处理方法
公开(公告)号：JP2010118718A
公开(公告)日：2010-05-27
申请号：JP2008288367
申请日：2008-11-11
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： SASAJIMA MASANORI
IPC分类号： H04N19/60 , H04N19/42 , H04N19/625
摘要： PROBLEM TO BE SOLVED: To solve the problem wherein in conventional data processing apparatuses are poor in versatility, because a dedicated circuit is equipped for each codec.
SOLUTION: This data processing apparatus includes a selector section 100, having a plurality of selector circuits 300 for selectively outputting any one signal from among input signals, including externally inputted signals and feedback signals from a unit section 101. The apparatus also includes a unit section, having operation circuits for processing one operation step in orthogonal transformation or inverse orthogonal transformation, based on a signal outputted from the selector section and outputting a feedback signal. The apparatus further includes a control section for outputting a first control signal controlling the selector section per operation step. With this circuit configuration, the versatile data processing apparatus capable of corresponding to each codec by switching the connection relationship can be provided.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题为了解决传统的数据处理设备的通用性差的问题，因为每个编解码器都配有专用电路。解决方案：该数据处理装置包括选择器部分100，其具有多个选择器电路300，用于从输入信号中选择性地输出任何一个信号，包括从外部输入的信号和来自单元部分101的反馈信号。该装置还包括单元部分，具有基于从选择器部分输出的信号并输出反馈信号的用于在正交变换或逆正交变换中处理一个操作步骤的操作电路。该装置还包括控制部分，用于输出每个操作步骤控制选择器部分的第一控制信号。利用该电路配置，可以提供能够通过切换连接关系而对应于每个编解码器的通用数据处理装置。版权所有（C）2010，JPO＆INPIT

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