专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08455942B2 Semiconductor device having vertical-type channel 有权
标题翻译：具有垂直型通道的半导体器件
公开(公告)号：US08455942B2
公开(公告)日：2013-06-04
申请号：US13085283
申请日：2011-04-12
申请人： Jung-Woo Park
发明人： Jung-Woo Park
IPC分类号： H01L29/772
CPC分类号： H01L29/7827 , H01L27/10873
摘要： A semiconductor device includes an active region including a surface region and a first recess formed below the surface region, the active region extending along a first direction; a device isolation structure provided on an edge of the active region; a gate line traversing over the surface region of the active region along a second direction orthogonal to the first direction; a second recess formed in the device isolation structure to receive a given portion of the gate line into the second recess; a first junction region formed in the active region beneath the first recess and on a first side of the gate line; and a second junction region formed on a second side of the gate line and above the first junction region. The first and second junction regions define a vertical-type channel that extends along lateral and vertical directions.
摘要翻译：半导体器件包括有源区，该有源区包括表面区域和形成在该表面区域下方的第一凹部，该有源区域沿第一方向延伸; 设置在所述有源区域的边缘上的器件隔离结构; 栅极线沿着与第一方向正交的第二方向横越有源区域的表面区域; 形成在所述器件隔离结构中以将栅极线的给定部分接收到第二凹部中的第二凹部; 形成在第一凹部下方的有源区域和栅极线的第一侧上的第一接合区域; 以及第二结区，形成在栅极线的第二侧并且在第一接合区的上方。第一和第二接合区限定沿着横向和垂直方向延伸的垂直型通道。

92. 发明授权

US08451037B2 Duty cycle correction circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US08451037B2
公开(公告)日：2013-05-28
申请号：US13048185
申请日：2011-03-15
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.
摘要翻译：占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比信号并输出检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

93. 发明授权

US08450772B2 Phase change RAM device and method for manufacturing the same 有权
标题翻译：相变RAM装置及其制造方法
公开(公告)号：US08450772B2
公开(公告)日：2013-05-28
申请号：US12362605
申请日：2009-01-30
申请人： Heon Yong Chang , Suk Kyoung Hong , Hae Chan Park
发明人： Heon Yong Chang , Suk Kyoung Hong , Hae Chan Park
IPC分类号： H01L29/02
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.
摘要翻译：相变RAM装置包括具有相变单元区域和电压施加区域的半导体基板; 依次形成在所述半导体衬底上的第一氧化物层，氮化物层和第二氧化物层; 形成在第一氧化物层中的第一插塞，相变单元区域的氮化物层和第二氧化物层; 形成在第一氧化物层和电压施加区域的氮化物层中的第二插塞; 形成在所述第二氧化物层中的导电线; 形成在所述第二氧化物层上的第三氧化物层; 形成为塞子的下部电极，所述下部电极形成为直接与所述第一插塞接触; 以及以图案形式依次形成在下电极上的相变层和上电极。

94. 发明授权

US08445989B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08445989B2
公开(公告)日：2013-05-21
申请号：US12956948
申请日：2010-11-30
申请人： Ba Wool Kim , Won Ho Shin
发明人： Ba Wool Kim , Won Ho Shin
IPC分类号： H01L27/10 , H01L29/00 , H01L23/58 , H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metal wiring which is formed over substructure; a first contact plug which is coupled to the first metal wiring and passes through a first interlayer insulating film provided over the substructure; a second metal wiring which is provided over the first interlayer insulating film and is coupled to the first contact plug; a second contact plug which is coupled to the second metal wiring and passes through a second interlayer insulating film which is provided over the first interlayer insulating film; and a fuse pattern and a data read fuse pattern which are coupled to the second contact plug and provided over the second interlayer insulating film.
摘要翻译：半导体器件包括形成在子结构上的第一金属布线; 第一接触插塞，其耦合到所述第一金属布线并且穿过设置在所述子结构上的第一层间绝缘膜; 第二金属布线，设置在所述第一层间绝缘膜上并耦合到所述第一接触插塞; 第二接触插塞，其耦合到所述第二金属布线并且穿过设置在所述第一层间绝缘膜上的第二层间绝缘膜; 以及熔丝图案和数据读取熔丝图案，其耦合到第二接触插塞并且设置在第二层间绝缘膜上。

95. 发明授权

US08445369B2 Method for fabricating semiconductor device 有权
公开(公告)号：US08445369B2
公开(公告)日：2013-05-21
申请号：US13244136
申请日：2011-09-23
申请人： Baek-Mann Kim
发明人： Baek-Mann Kim
IPC分类号： H01L21/265
CPC分类号： H01L21/28525 , H01L21/76877 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.

96. 发明申请

US20130121097A1 ADDRESS OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：地址输出电路和半导体存储器件
公开(公告)号：US20130121097A1
公开(公告)日：2013-05-16
申请号：US13411551
申请日：2012-03-03
申请人： Sang Il PARK
发明人： Sang Il PARK
IPC分类号： G11C29/04
CPC分类号： G11C29/76 , G11C29/34 , G11C2029/1202
摘要： A semiconductor memory device includes a signal generation unit configured to generate a toggling signal and first and second pulse signals in response to a test signal and a burst pulse signal. An address output unit may be configured to receive first to fourth input addresses and output sequentially first to fourth output addresses in response to the toggling signal and the first and second pulse signals. A repair unit may be configured to perform a repair operation on a word line selected by the first to fourth output addresses.
摘要翻译：半导体存储器件包括：信号生成单元，被配置为响应于测试信号和突发脉冲信号产生切换信号和第一和第二脉冲信号。地址输出单元可以被配置为响应于切换信号和第一和第二脉冲信号而接收第一至第四输入地址并且顺序地输出第一至第四输出地址。维修单元可以被配置为对由第一至第四输出地址选择的字线执行修复操作。

97. 发明申请

US20130119545A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20130119545A1
公开(公告)日：2013-05-16
申请号：US13347570
申请日：2012-01-10
申请人： Un Hee LEE
发明人： Un Hee LEE
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L27/10885 , H01L27/10888
摘要： A semiconductor device and a method for forming the same are disclosed, which can protect a polysilicon layer of a bit line contact plug even when a critical dimension (CD) of the bit line is reduced by a fabrication change, thereby preventing defective resistivity caused by a damaged bit line contact plug from being generated. The semiconductor device includes one or more interlayer insulation film patterns formed over a semiconductor substrate, a bit line contact plug formed over the semiconductor substrate between the interlayer insulation films, and located below a top part of the interlayer insulation film pattern, and a bit line formed over the bit line contact plug.
摘要翻译：公开了一种半导体器件及其形成方法，即使当通过制造变化减小位线的临界尺寸（CD）时，也可以保护位线接触插塞的多晶硅层，从而防止由产生损坏的位线接触插头。半导体器件包括在半导体衬底上形成的一个或多个层间绝缘膜图案，形成在半导体衬底之间的层间绝缘膜之间并且位于层间绝缘膜图案的顶部下方的位线接触插塞和位线形成在位线接触插头上。

98. 发明申请

US20130119462A1 SEMICONDUCTOR DEVICE FOR INCREASING BIT LINE CONTACT AREA, AND MODULE AND SYSTEM INCLUDING THE SAME 有权
标题翻译：用于增加位线接触区域的半导体器件以及包括它们的模块和系统
公开(公告)号：US20130119462A1
公开(公告)日：2013-05-16
申请号：US13347614
申请日：2012-01-10
申请人： Jung Seob KYE , Jung Min Han
发明人： Jung Seob KYE , Jung Min Han
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L27/10823 , H01L27/10876 , H01L27/10888
摘要： A semiconductor device including a buried gate is disclosed. In the semiconductor device, a bit line contact contacts a top surface and lateral surfaces of an active region, such that a contact area between a bit line contact and the active region is increased and a high-resistivity failure is prevented from occurring in a bit line contact.
摘要翻译：公开了一种包括掩埋栅极的半导体器件。在半导体器件中，位线接触接触有源区的顶表面和侧表面，使得位线接触和有源区之间的接触面积增加，并且防止在位中发生高电阻率故障线接触。

99. 发明授权

US08441100B2 Capacitor with pillar type storage node and method for fabricating the same 有权
标题翻译：具有支柱式存储节点的电容器及其制造方法
公开(公告)号：US08441100B2
公开(公告)日：2013-05-14
申请号：US13069280
申请日：2011-03-22
申请人： Kee-Jeung Lee , Han-Sang Song , Deok-Sin Kil , Young-Dae Kim , Jin-Hyock Kim , Kwan-Woo Do , Kyung-Woong Park
发明人： Kee-Jeung Lee , Han-Sang Song , Deok-Sin Kil , Young-Dae Kim , Jin-Hyock Kim , Kwan-Woo Do , Kyung-Woong Park
IPC分类号： H01L21/02
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/90
摘要： A capacitor includes a pillar-type storage node, a supporter disposed entirely within an inner empty crevice of the storage node, a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the inner empty crevice, a dielectric layer over the storage node, and a plate node over the dielectric layer.
摘要翻译：一种电容器包括：柱状存储节点，完全位于存储节点的内部空缝隙内的支撑件，在支撑件上方的导电覆盖层，并与存储节点接触，以密封内部空缝隙的入口;电介质存储节点上的平板节点以及电介质层上的平板节点。

100. 发明授权

US08441079B2 Semiconductor device with gate stack structure 有权
公开(公告)号：US08441079B2
公开(公告)日：2013-05-14
申请号：US13043385
申请日：2011-03-08
申请人： Kwan-Yong Lim , Hong-Seon Yang , Heung-Jae Cho , Tae-Kyung Kim , Yong-Soo Kim , Min-Gyu Sung
发明人： Kwan-Yong Lim , Hong-Seon Yang , Heung-Jae Cho , Tae-Kyung Kim , Yong-Soo Kim , Min-Gyu Sung
IPC分类号： H01L29/423 , H01L29/788
CPC分类号： H01L29/4925 , H01L21/28061 , H01L29/42324 , H01L29/4941 , H01L29/513 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式