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1. 发明授权

US08605496B2 Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof 有权
标题翻译：用于将数据同时写入多个单元的半导体存储器件及其刷新方法
公开(公告)号：US08605496B2
公开(公告)日：2013-12-10
申请号：US13152692
申请日：2011-06-03
申请人： Hee Bok Kang , Suk Kyoung Hong
发明人： Hee Bok Kang , Suk Kyoung Hong
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C8/06 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C16/3431 , G11C2013/0052 , G11C2013/0078 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/72 , G11C2213/75 , G11C2213/76
摘要： A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.
摘要翻译：半导体存储器件包括被配置为提供单元驱动电压的读/写位线。选择单元连接到读/写位线并由字线控制。多个单元连接在选择单元和源极线之间，并且单元被配置为根据单元驱动电压来读取和写入数据。多个开关元件的每个开关元件与多个单元的单个单元并联连接，并且多个开关元件由多个位线选择性地控制。

2. 发明授权

US08274369B2 Radio frequency identification device having nonvolatile ferroelectric memory 有权
标题翻译：具有非易失性铁电存储器的射频识别装置
公开(公告)号：US08274369B2
公开(公告)日：2012-09-25
申请号：US12147675
申请日：2008-06-27
申请人： Hee Bok Kang , Jin Hong An , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Suk Kyoung Hong
IPC分类号： H04Q5/22
CPC分类号： H04Q9/00 , H04Q2209/47 , H04Q2209/84
摘要： A RFID device having a nonvolatile ferroelectric memory includes an analog block. A power-on reset unit configured to sense a power voltage and output a power sensing signal is included in the analog block. A radio frequency signal sensing unit is configured to sense the level of a detecting signal corresponding to a radio frequency signal received by the antenna of the RFID device and outputs a radio frequency sensing signal. A power-on reset mixer is configured to synthesize the power sensing signal and the radio frequency sensing signal and outputs a power-on reset signal according to the voltage levels of the power sensing signal and the radio frequency sensing signal.
摘要翻译：具有非易失性铁电存储器的RFID装置包括模拟块。配置为感测电源电压并输出功率感测信号的上电复位单元包括在模拟块中。射频信号感测单元被配置为感测与由RFID设备的天线接收的射频信号相对应的检测信号的电平，并输出射频感测信号。上电复位混频器被配置为合成功率感测信号和射频感测信号，并根据功率检测信号和射频感测信号的电压电平输出上电复位信号。

3. 发明授权

US08194440B2 Phase change memory device having multiple reset signals and operating method thereof 有权
标题翻译：具有多个复位信号的相变存储器件及其操作方法
公开(公告)号：US08194440B2
公开(公告)日：2012-06-05
申请号：US12133725
申请日：2008-06-05
申请人： Hee Bok Kang , Suk Kyoung Hong
发明人： Hee Bok Kang , Suk Kyoung Hong
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/008 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory device includes a cell array unit having a phase change resistance cell positioned at an intersection of a word line and a bit line. A write driving unit is configured to generate a single write voltage to the cell array unit when data to be written is a first data and is configured to generate a plurality of write voltages selectively when the data is a second data.
摘要翻译：相变存储器件包括具有位于字线和位线的交点处的相变电阻单元的单元阵列单元。写入驱动单元被配置为当要写入的数据是第一数据时，向单元阵列单元生成单个写入电压，并且被配置为当数据是第二数据时选择性地生成多个写入电压。

4. 发明授权

US07969794B2 One-transistor type DRAM 失效
标题翻译：单晶体管型DRAM
公开(公告)号：US07969794B2
公开(公告)日：2011-06-28
申请号：US12575343
申请日：2009-10-07
申请人： Hee Bok Kang , Jin Hong An , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Suk Kyoung Hong
IPC分类号： G11C7/10
CPC分类号： H01L27/10802 , G11C11/404 , G11C2211/4016 , H01L27/10844 , H01L29/7841
摘要： A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.
摘要翻译：包括连接在位线和源极线之间并由字线控制的浮体存储元件的单晶体管型DRAM包括排列成行方向的多条源极线和字线，列方向，沿列方向布置的多个钳位位线和参考位线，包括浮体存储元件并形成在源极线，字线和位线交叉的区域中的单元阵列，钳位包括浮体存储元件并形成在源极线，字线和位线交叉的区域的单元阵列，包括浮体存储元件的参考单元阵列，并形成在源极线，字线线和位线交叉，读出放大器和写入驱动单元连接到位线并被配置为接收钳位电压和参考电压。

5. 发明授权

US07939365B2 Phase change memory device, manufacturing method thereof and operating method thereof 有权
标题翻译：相变存储器件及其制造方法及其操作方法
公开(公告)号：US07939365B2
公开(公告)日：2011-05-10
申请号：US12134388
申请日：2008-06-06
申请人： Hee Bok Kang , Suk Kyoung Hong
发明人： Hee Bok Kang , Suk Kyoung Hong
IPC分类号： H01L21/44
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change memory (PCM) device, a manufacturing technique of making the PCM device, and a way of operating the PCM device is presented. The PCM device is structured to have a silicon on insulator type substrate that provides an advantage of thermally insulating the active area of the PCM device without the need for an additional insulation layer. The PCM device has a phase change resistor PCR that has one terminal connected to a word line and the other terminal connected in common to the N-terminals of two PN diodes in which the P-terminals are connected in common to the bit line. As a result, a current flowing through the phase change resistor PCR is doubled which results in doubling the cell driving capacity.
摘要翻译：提出了相变存储器（PCM）装置，制造PCM装置的制造技术以及操作PCM装置的方法。 PCM器件被构造为具有绝缘体上硅型衬底，其提供了对PCM器件的有源区域进行热绝缘的优点，而不需要额外的绝缘层。 PCM装置具有一个相变电阻器PCR，其一个端子连接到字线，另一个端子共同连接到两个PN二极管的N端，其中P端子共同连接到位线。结果，流过相变电阻器PCR的电流加倍，导致电池驱动能力增加一倍。

6. 发明授权

US07929339B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07929339B2
公开(公告)日：2011-04-19
申请号：US12645704
申请日：2009-12-23
申请人： Hee Bok Kang , Jin Hong An , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Suk Kyoung Hong
IPC分类号： C11C11/00
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage.
摘要翻译：相变存储器件包括沿行方向布置的多个字线和沿列方向布置的多个位线。多个基准位线和多个钳位位线在列方向上排列。布置包括相变电阻单元的单元阵列块，其中字线和位线相交。形成参考单元阵列块，其中字线和参考位线相交。参考单元阵列块被配置为输出参考电流。形成钳位单元阵列块，其中字线和钳位位线相交。钳位单元阵列块被配置为输出钳位电流。感测放大器连接到每个位线，并且被配置为接收钳位电压和参考电压。

7. 发明授权

US07864611B2 One-transistor type DRAM 失效
标题翻译：单晶体管型DRAM
公开(公告)号：US07864611B2
公开(公告)日：2011-01-04
申请号：US12609649
申请日：2009-10-30
申请人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
IPC分类号： G11C7/02
CPC分类号： G11C11/404 , G11C11/4091 , G11C11/4096 , G11C11/4099 , G11C2211/4016
摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.
摘要翻译：单晶体管型DRAM包括连接在位线和源极线之间并由字线控制的浮体存储元件。 DRAM包括沿行方向布置的多个源极线和字线，沿列方向布置的多个位线，沿列方向布置的多个参考位线，包括浮体存储元件的单元阵列和形成在源极线，字线和位线交叉的区域中，形成在源极线，字线和位线交叉配置的区域中的包括浮体存储元件的基准单元阵列输出具有多个电平的参考电流;多个参考电压产生单元，连接到参考位线并被配置为产生与具有多个电平的参考电流相对应的多个参考电压;以及读出放大器和写入驱动单元连接到位线并被配置为接收多个参考电压。

8. 发明授权

US07791934B2 Method for driving multi-level data to a phase change memory device 有权
标题翻译：将多级数据驱动到相变存储器件的方法
公开(公告)号：US07791934B2
公开(公告)日：2010-09-07
申请号：US12146559
申请日：2008-06-26
申请人： Hee Bok Kang , Suk Kyoung Hong
发明人： Hee Bok Kang , Suk Kyoung Hong
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0076 , G11C2013/008 , G11C2013/009 , G11C2013/0092 , G11C2211/5634 , G11C2213/72
摘要： A phase change memory device including a phase change resistor senses a crystallization state that is changed according to supplied currents to store data corresponding to the crystallization state. The phase change memory device may receive and store multi-level data. The multi-level data is driven to the phase change memory device by reading cell data of a selected cell. The cell data is compared to multi-level data to be written to the cell. A high resistance reset state is written to the phase change resistor by applying a write voltage that corresponds to a threshold voltage when the cell data is different from the multi-level data. The multi-level data is then written to the phase change resistor by writing and verifying a set state that corresponds to the multi-level data.
摘要翻译：包括相变电阻器的相变存储器件感测根据所提供的电流而改变的结晶状态，以存储对应于结晶状态的数据。相变存储器装置可以接收和存储多级数据。多级数据通过读取所选择的单元的单元数据被驱动到相变存储器件。将单元数据与要写入单元的多级数据进行比较。当电池数据不同于多电平数据时，通过施加与阈值电压相对应的写入电压，将高电阻复位状态写入相变电阻器。然后通过写入和验证与多级数据相对应的设置状态将多电平数据写入相变电阻器。

9. 发明授权

US07724569B2 1-transistor type DRAM driving method with an improved write operation margin 失效
标题翻译： 1晶体管型DRAM驱动方法具有改进的写操作余量
公开(公告)号：US07724569B2
公开(公告)日：2010-05-25
申请号：US12166753
申请日：2008-07-02
申请人： Hee Bok Kang , Suk Kyoung Hong
发明人： Hee Bok Kang , Suk Kyoung Hong
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C11/4085 , G11C11/4094 , G11C2211/4016
摘要： A 1-transistor type DRAM driving process writes a data bit that corresponds to a level applied to a bit line. A first hold period holds data by deactivating a word line of an NMOS transistor and precharging a source and bit line. After the first hold period, a complex operation period operates the NMOS transistor and a bipolar transistor by activating the word line of the NMOS transistor, shifting the source line voltage to a ground voltage, and shifting the bit line voltage to a corresponding multi level bit voltage level. After the complex operation period, a bipolar transistor operation period operates only the bipolar transistor by deactivating the word line of the NMOS transistor. After the bipolar transistor operation period, a second hold period holds the data by precharging the source and bit lines of the NMOS transistor and the bit level applied to the bit line is written.
摘要翻译： 1晶体管型DRAM驱动处理将与应用于位线的电平对应的数据位写入。第一保持周期通过去激活NMOS晶体管的字线并预充电源极和位线来保持数据。在第一保持周期之后，复合工作周期通过激活NMOS晶体管的字线来操作NMOS晶体管和双极晶体管，将源极线电压移动到接地电压，并将位线电压移位到相应的多电平位电压电平。在复杂操作周期之后，双极晶体管工作周期仅通过使NMOS晶体管的字线去激活来操作双极晶体管。在双极晶体管工作周期之后，第二保持周期通过对NMOS晶体管的源极和位线进行预充电来保持数据，并且写入施加到位线的位电平。

10. 发明授权

US07643336B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07643336B2
公开(公告)日：2010-01-05
申请号：US11987758
申请日：2007-12-04
申请人： Hee Bok Kang , Jin Hong An , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Suk Kyoung Hong
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2213/72
摘要： A phase change memory device comprises a cell array unit including a phase change resistance cell disposed in a region where a word line and a bit line are crossed, a sense amplifier configured to sense and amplify data of the phase change resistance cell, a write driving unit configured to supply a write voltage corresponding to data to be written in the cell array unit in response to an enabling signal, and a write verifying control unit controlled by an activation control signal and configured to compare data read through the sense amplifier with the data to be written so as to output the enabling signal.
摘要翻译：相变存储器件包括：单元阵列单元，包括设置在字线和位线交叉的区域中的相变电阻单元，被配置为感测和放大相变电阻单元的数据的读出放大器，写入驱动单元，被配置为响应于使能信号提供与要写入单元阵列单元的数据相对应的写入电压;以及写入验证控制单元，其由激活控制信号控制，并且被配置为将通过读出放大器读取的数据与数据进行比较被写入以输出使能信号。

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