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1. 发明授权

US08780621B2 Semiconductor integrated circuit system and method for driving the same 有权
公开(公告)号：US08780621B2
公开(公告)日：2014-07-15
申请号：US13326907
申请日：2011-12-15
申请人： Hae Chan Park , Soo Gil Kim
发明人： Hae Chan Park , Soo Gil Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/00 , G11C13/0004 , G11C13/0033 , G11C2013/0092 , Y10S977/754
摘要： A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area.

2. 发明授权

US08445880B2 Phase change memory device having bit-line discharge block and method of fabricating the same 有权
标题翻译：具有位线放电模块的相变存储器件及其制造方法
公开(公告)号：US08445880B2
公开(公告)日：2013-05-21
申请号：US12635920
申请日：2009-12-11
申请人： Hae Chan Park
发明人： Hae Chan Park
IPC分类号： H01L29/02 , H01L47/00 , H01L21/82
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A phase change memory device capable of fully discharging bit lines, even while occupying a relatively small area, and a fabricating method thereof are presented. The phase change memory device includes a semiconductor substrate, a word line area, a discharge line area, a switching PN diode, a dummy PN diode, a phase change structure, and a bit line. The word line area is formed in a memory cell area of the semiconductor substrate. The discharge line area is formed in the bit-line discharge area of the semiconductor substrate. The switching PN diode is formed on the word line area. The dummy PN diode is formed on the discharge line area. The phase change structure is formed on the switching PN diode and is electrically connected to the switching diode. The bit line is electrically connected to the phase change structure and the dummy PN diode.
摘要翻译：提出即使占据相对小的面积也能够完全放电位线的相变存储器件及其制造方法。相变存储器件包括半导体衬底，字线区域，放电线区域，开关PN二极管，虚拟PN二极管，相变结构和位线。字线区域形成在半导体衬底的存储单元区域中。放电线区域形成在半导体衬底的位线放电区域中。开关PN二极管形成在字线区域上。虚拟PN二极管形成在放电线区域上。相变结构形成在开关PN二极管上并与开关二极管电连接。位线电连接到相变结构和伪PN二极管。

3. 发明授权

US08008167B2 Phase change memory device having an increased sensing margin for cell efficiency and method for manufacturing the same 有权
标题翻译：具有增加的用于电池效率的感测裕度的相变存储器件及其制造方法
公开(公告)号：US08008167B2
公开(公告)日：2011-08-30
申请号：US12436515
申请日：2009-05-06
申请人： Hae Chan Park
发明人： Hae Chan Park
IPC分类号： H01L21/20 , H01L45/00
CPC分类号： H01L45/126 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1666
摘要： A phase change memory device having an increased sensing margin for improved cell efficiency. The phase change memory device includes a plurality of diodes formed in an active region of a semiconductor substrate; an insulation layer pattern formed on the respective diodes; a phase change layer formed on the insulation layer pattern in such a way as not to be electrically connected with the diodes; bit lines formed over the phase change layer; and a global X-decoder line formed over the bit lines. The present invention suppresses current flow in a phase change memory device because the dummy cell string and the dummy active region are not electrically connected with each other under the global X-decoder line, whereby preventing parasitic current from being produced in the phase change memory device.
摘要翻译：一种具有增加的感测余量以提高电池效率的相变存储器件。相变存储器件包括形成在半导体衬底的有源区中的多个二极管; 形成在各个二极管上的绝缘层图案; 形成在绝缘层图案上以不与二极管电连接的方式的相变层; 形成在相变层上的位线; 以及在位线上形成的全局X解码器线。本发明抑制了相变存储器件中的电流流动，因为虚拟单元串和虚设有源区在全局X解码器线下不彼此电连接，从而防止在相变存储器件中产生寄生电流。

4. 发明申请

US20110143477A1 METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE 有权
标题翻译：使用交叉图形技术制造相位变化记忆装置的方法
公开(公告)号：US20110143477A1
公开(公告)日：2011-06-16
申请号：US12834141
申请日：2010-07-12
申请人： Jang Uk LEE , Kang Sik CHOI , Hae Chan PARK , Jin Hyock KIM , Ja Chun KU
发明人： Jang Uk LEE , Kang Sik CHOI , Hae Chan PARK , Jin Hyock KIM , Ja Chun KU
IPC分类号： H01L21/28
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.
摘要翻译：提供一种制造相变存储器件的方法。在半导体衬底上形成具有以恒定距离隔开的多个金属字线的第一绝缘层。形成具有阻挡金属层，多晶硅层和硬掩模层的多个线结构以覆盖在多个金属字线上。在线路结构之间形成第二绝缘层。通过使用与金属字线交叉的掩模图案蚀刻线结构的硬掩模层和多晶硅层来形成交叉图案。第三绝缘层埋在交叉图案之间的空间内。形成自对准的相变接触孔，同时，通过选择性地去除构成交叉图案的硬掩模层，形成由剩余多晶硅层形成的二极管图案。

5. 发明申请

US20110075473A1 CIRCUIT AND METHOD FOR GENERATING REFERENCE VOLTAGE, PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND READ METHOD USING THE SAME 有权
标题翻译：用于产生参考电压，相位变化随机存取存储器装置的电路和方法及使用其的读取方法
公开(公告)号：US20110075473A1
公开(公告)日：2011-03-31
申请号：US12648437
申请日：2009-12-29
申请人： Hae Chan PARK , Se Ho LEE , Soo Gil KIM
发明人： Hae Chan PARK , Se Ho LEE , Soo Gil KIM
IPC分类号： G11C11/00 , G11C7/02 , G11C5/14
CPC分类号： G11C7/14 , G11C5/147 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C2013/0054 , G11C2211/5634
摘要： A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write driver writes data to the reference cell. The reference cell sense amplifier reads out the data stored in the reference cell on the basis of a predetermined reference voltage. A voltage compensation unit outputs a compensation reference voltage by controlling the reference voltage in accordance with the output value of the sense amplifier.
摘要翻译：用于产生参考电压的电路包括至少一个参考单元，参考单元写入驱动器，参考单元读出放大器和电压补偿单元。参考单元是可变电阻存储单元。参考单元写入驱动程序将数据写入参考单元。参考单元读出放大器基于预定的参考电压读出存储在参考单元中的数据。电压补偿单元通过根据读出放大器的输出值控制参考电压来输出补偿基准电压。

6. 发明申请

US20100327251A1 PHASE CHANGE MEMORY DEVICE HAVING PARTIALLY CONFINED HEATING ELECTRODES CAPABLE OF REDUCING HEATING DISTURBANCES BETWEEN ADJACENT MEMORY CELLS 审中-公开
标题翻译：具有能够减少相邻存储器单元之间的加热干扰的部分限制加热电极的相变存储器件
公开(公告)号：US20100327251A1
公开(公告)日：2010-12-30
申请号：US12647595
申请日：2009-12-28
申请人： Hae Chan PARK
发明人： Hae Chan PARK
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： A phase change memory device having partially confined heating electrodes capable of reducing thermal disturbances between adjacent memory cells is presented. The phase change memory device includes a plurality of active regions, a plurality of switching elements, a plurality of heating electrodes, and a plurality of phase change structure lines. The active regions being linear and parallel to each other. The switching elements are coupled to the active regions. The heating electrodes are on and coupled to the switching elements. The phase change structure lines are coupled to the heating electrodes such that the phase change structure lines are substantially vertical to the active regions. The phase change structure lines includes a plurality of plugs projecting downwards that couple to overlapped portions of the heating electrodes.
摘要翻译：提出了具有能够减少相邻存储单元之间的热扰动的部分限制的加热电极的相变存储器件。相变存储器件包括多个有源区，多个开关元件，多个加热电极和多个相变结构线。有源区域是线性的并且彼此平行。开关元件耦合到有源区域。加热电极接通并耦合到开关元件。相变结构线耦合到加热电极，使得相变结构线基本上垂直于有源区。相变结构线包括向下突出的多个插头，其耦合到加热电极的重叠部分。

7. 发明授权

US07024985B2 Coffee extracting apparatus for a coffee machine 失效
标题翻译：咖啡机咖啡提取装置
公开(公告)号：US07024985B2
公开(公告)日：2006-04-11
申请号：US10444377
申请日：2003-05-23
申请人： Hae Chan Park
发明人： Hae Chan Park
IPC分类号： A47J31/34
CPC分类号： A47J31/3619 , A47J31/3614
摘要： A coffee extracting apparatus for a coffee machine, which allows easy extraction of coffee liquid and easy removal of coffee grinds, is disclosed. The coffee extracting apparatus includes a machine case, a hopper receiving coffee grinds, a cylinder unit disposed below the hopper and rotated within a certain angle range, a upper piston movably inserted in the cylinder unit and having a hot water path therein, a lower piston inserted in the cylinder unit to press coffee grinds against the upper piston and having coffee discharge paths therein, cam and link members to guide movement of the cylinder, the upper piston and the lower piston, and a drive unit mounted on the machine case to supply driving force to the cam members. The coffee extracting apparatus is easily removed from the coffee machine. A unit amount of coffee liquid is extracted every revolution of the drive unit. Since hot water to be mixed with coffee grinds is supplied to the lower piston from the upper piston, adhesion of coffee grinds on a bottom surface of the upper piston is avoided.
摘要翻译：公开了一种用于咖啡机的咖啡提取装置，其允许容易地提取咖啡液体并且容易地去除咖啡研磨物。咖啡提取装置包括机壳，容纳咖啡研磨斗的料斗，设置在料斗下方并在一定角度范围内旋转的缸单元，可活动地插入缸单元中并具有热水通道的上活塞，下活塞插入气缸单元中，将咖啡研磨件压靠在上活塞上并具有咖啡排放路径，凸轮和连杆构件以引导气缸，上活塞和下活塞的运动，以及安装在机壳上的驱动单元对凸轮部件的驱动力。咖啡提取装置容易从咖啡机中取出。在驱动单元的每转一次提取单位量的咖啡液。由于与咖啡研磨机混合的热水从上活塞供给到下活塞，因此避免了咖啡研磨机在上活塞的底面上的粘附。

8. 发明授权

US08570796B2 Nonvolatile memory cell, nonvolatile memory device and method for driving the same 有权
标题翻译：非易失性存储单元，非易失性存储器件及其驱动方法
公开(公告)号：US08570796B2
公开(公告)日：2013-10-29
申请号：US13619672
申请日：2012-09-14
申请人： Hae-Chan Park , Gap-Sok Do , Jang-Uk Lee
发明人： Hae-Chan Park , Gap-Sok Do , Jang-Uk Lee
IPC分类号： G11C11/00
CPC分类号： G11C16/3431 , G11C13/0004 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2213/71 , G11C2213/75 , G11C2213/76 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1226 , H01L45/1286 , H01L45/144 , H01L45/148
摘要： A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.
摘要翻译：非易失性存储单元能够通过采用硫化物化合物用于通道的双栅结构来减小每单位面积的尺寸。所述非易失性存储单元包括相变层，第一和第二栅极，所述相变层与所述相变层的侧面相接触，以跨过所述相变层，并且控制流经所述相变的电流每个栅极的层被布置成独立于另一个栅极引起相变层的相变。

9. 发明授权

US08384057B2 Phase-change memory device having multiple diodes 有权
标题翻译：具有多个二极管的相变存储器件
公开(公告)号：US08384057B2
公开(公告)日：2013-02-26
申请号：US12976676
申请日：2010-12-22
申请人： Hae Chan Park
发明人： Hae Chan Park
IPC分类号： H01L45/00
CPC分类号： H01L27/2409 , H01L29/861 , H01L45/06
摘要： A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer.
摘要翻译：提供了具有改善的电流特性的相变存储器件。相变存储器件包括金属字线，与金属字线接触的第一导电类型的半导体层和与金属字线和半导体层接触的辅助二极管层。

10. 发明申请

US20130039123A1 NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME 有权
公开(公告)号：US20130039123A1
公开(公告)日：2013-02-14
申请号：US13619672
申请日：2012-09-14
申请人： Hae-Chan PARK , Gap-Sok Do , Jang-Uk Lee
发明人： Hae-Chan PARK , Gap-Sok Do , Jang-Uk Lee
IPC分类号： G11C11/00
CPC分类号： G11C16/3431 , G11C13/0004 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2213/71 , G11C2213/75 , G11C2213/76 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1226 , H01L45/1286 , H01L45/144 , H01L45/148
摘要： A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.

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