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91. 发明授权

US09383766B2 Chip performance monitoring system and method 有权
标题翻译：芯片性能监控系统及方法
公开(公告)号：US09383766B2
公开(公告)日：2016-07-05
申请号：US13737168
申请日：2013-01-09
申请人： International Business Machines Corporation
发明人： Margaret R. Charlebois , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Tad J. Wilder
IPC分类号： G06F11/30 , G06F1/08 , G06F11/34 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31727 , G01R31/318577 , G06F1/08 , G06F11/348
摘要： Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.
摘要翻译：公开了一种芯片性能监视系统，方法和计算机程序产品，其中性能监视器输出信号通过相邻扫描链传播，以避免信号降级入射到高频信号的跨芯片传输。由于用于控制通过扫描链的信号传播的时钟信号频率通常将小于性能监视器输出信号频率的两倍，因此会发生具有混叠的频率子采样。为了补偿，可以在不同的时间周期期间使用具有不同时钟信号频率的不同时钟信号来控制通过扫描链的信号传播，并且在这些不同的时间周期期间，可以在扫描链的输出节点捕获不同的数据输出。可以测量这些不同数据输出的数据输出频率，并且可以基于给定不同时钟信号频率的不同数据输出频率来确定性能监视器输出信号频率。

92. 发明授权

US09373678B2 Non-planar capacitors with finely tuned capacitance values and methods of forming the non-planar capacitors 有权
标题翻译：具有微调电容值的非平面电容器和形成非平面电容器的方法
公开(公告)号：US09373678B2
公开(公告)日：2016-06-21
申请号：US14306294
申请日：2014-06-17
申请人： International Business Machines Corporation
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/20 , H01L27/06 , H01L49/02 , H01L29/78 , H01L29/66 , H01L21/308 , H01L21/84 , H01L27/12
CPC分类号： H01L28/40 , H01L21/3086 , H01L21/845 , H01L27/0629 , H01L27/1207 , H01L28/60 , H01L28/91 , H01L29/66795 , H01L29/785
摘要： Disclosed are non-planar capacitors with finely tuned capacitances and methods of forming them. The capacitors each incorporate one or more semiconductor bodies and one or more gate stacks traversing the one or more semiconductor bodies. At least one first semiconductor body is etched so that it is shorter in length than the others, which are incorporated into other non-planar devices and/or into the same non-planar capacitor. Additionally, at least one gate stack can be formed so that it traverses a first portion and, particularly, an end portion of the shortened semiconductor body and further so that it extends laterally some distance beyond that first portion. In such capacitors, the length of the first portion of the shorted semiconductor body, which corresponds to a capacitor conductor and which is traversed by the gate stack, which corresponds to a capacitor dielectric and another capacitor conductor, is predetermined to achieve a desired capacitance.
摘要翻译：公开了具有微调电容的非平面电容器及其形成方法。电容器各自包括一个或多个半导体本体和穿过一个或多个半导体主体的一个或多个栅极叠层。蚀刻至少一个第一半导体本体，使得其长度比其它半导体本体短，其被并入其它非平面器件和/或并入相同的非平面电容器中。此外，可以形成至少一个栅极堆叠，使得其穿过第一部分，特别是穿过缩短的半导体本体的端部，并且进一步使其横向延伸超过该第一部分一段距离。在这种电容器中，对应于电容器导体的电容器导体的对应于电容器电介质和另一个电容器导体的电容器导体的短路半导体本体的第一部分的长度被预先确定以获得所需的电容。

93. 发明授权

US09343185B2 Electronic circuit for fitting a virtual address range to a physical memory containing faulty address 有权
标题翻译：用于将虚拟地址范围拟合到包含故障地址的物理存储器的电子电路
公开(公告)号：US09343185B2
公开(公告)日：2016-05-17
申请号：US14037487
申请日：2013-09-26
申请人： International Business Machines Corporation
发明人： John E. Barth, Jr. , Srivatsan Chellappa , Dean L. Lewis
IPC分类号： G06F12/00 , G11C29/00 , G06F9/445 , G06F9/32 , G06F12/08 , G06F11/10 , G06F12/12 , G06F12/06 , G06F13/22 , G06F13/38 , G06F12/10 , G06F12/04 , G11C15/00 , G11C8/06
CPC分类号： G11C29/76 , G06F8/65 , G06F9/328 , G06F11/1008 , G06F12/04 , G06F12/0638 , G06F12/0868 , G06F12/0886 , G06F12/1027 , G06F12/109 , G06F12/126 , G06F13/225 , G06F13/385 , G11C8/06 , G11C15/00
摘要： A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.
摘要翻译：具有可变大小的故障存储器地址块的存储器连接到存储器中存储地址范围的数据值的TCAM。地址范围对应于与偏移相结合的虚拟地址，远离失败的存储器地址。连接到TCAM的还原电路基于虚拟地址产生每个编程的地址范围的输出。连接到还原电路的优先编码器从缩小电路中选择第一范围，并将第一范围传递给随机存取存储器（RAM）。响应虚拟地址将地址置于地址范围之一中，优先级编码器将包含虚拟地址的第一范围传递给RAM，RAM根据第一范围将相应的偏移值传递给加法器。 Adder计算一个物理内存地址，将虚拟地址指向功能内存位置。

94. 发明授权

US09337724B2 Load sensing voltage charge pump system 有权
标题翻译：负载感应电压电荷泵系统
公开(公告)号：US09337724B2
公开(公告)日：2016-05-10
申请号：US14083781
申请日：2013-11-19
申请人： GLOBALFOUNDRIES INC.
发明人： Christopher P. Miller
IPC分类号： H02M3/07 , H02M1/00
CPC分类号： H02M3/073 , H02M2001/0032 , H02M2003/077 , Y02B70/16
摘要： A load-sensing voltage charge pump system may include a plurality of reference voltage inputs including a target voltage input. The system may also include a plurality of voltage charge pump segments equal in number to the plurality of reference voltage inputs. A voltage charge pump segment may include: a regulator that receives a reference voltage, and a voltage charge pump that outputs a current to a load at a sensed voltage. The regulator may enable each of the voltage charge pump segments, when the sensed voltage is less than or equal to the one of the reference voltages and the target voltage. The system may include a boosted line connected in parallel to an output of each of the voltage charge pump segments. The boosted line may receive the current at the sensed voltage from each of the voltage charge pump segments that is enabled.
摘要翻译：负载感测电压电荷泵系统可以包括包括目标电压输入的多个参考电压输入。该系统还可以包括与多个参考电压输入数量相等的多个电压电荷泵段。电压电荷泵段可以包括：接收参考电压的调节器和在感测电压下将电流输出到负载的电压电荷泵。当感测到的电压小于或等于参考电压和目标电压之一时，调节器可以使得每个电压电荷泵段。该系统可以包括与每个电压电荷泵段的输出并联连接的升压线。升压线路可以从启用的每个电压电荷泵分段接收感测电压的电流。

95. 发明授权

US09337173B2 Three-dimensional inter-chip contact through vertical displacement MEMS 有权
公开(公告)号：US09337173B2
公开(公告)日：2016-05-10
申请号：US14826261
申请日：2015-08-14
申请人： International Business Machines Corporation
发明人： Kenneth J. Goodnow , Todd E. Leonard , Stephen G. Shuma , Peter A. Twombly
IPC分类号： H01L25/065 , H01L21/00 , H01H59/00 , H01L23/528 , H01L23/538 , B81B3/00 , H01L25/00 , B81C1/00
CPC分类号： H01L25/0657 , B81B3/0056 , B81B3/0086 , B81C1/00158 , B81C1/00182 , B81C1/00198 , H01H59/0009 , H01L23/528 , H01L23/5386 , H01L23/5389 , H01L25/50 , H01L2225/06527 , H01L2924/0002 , H01L2924/1434 , H01L2924/1461 , H01L2924/00
摘要： An electrically conducting, vertically displacing microelectromechanical system (MEMS) is formed on a first integrated circuit chip. The first integrated circuit chip is physically connected to a three-dimensional packaging structure. The three-dimensional packaging structure maintains a fixed distance between the first integrated circuit chip and a second integrated circuit chip. A control circuit is operatively connected to the MEMS. The control circuit directs movement of the MEMS between a first position and a second position. The MEMS makes contact with a contact pad on the second integrated circuit chip when it is in the second position forming a conductive path and providing electrical communication between the first integrated circuit chip and the second integrated circuit chip. The MEMS avoids making contact with the contact pad on the second integrated circuit chip when it is in the first position.

96. 发明授权

US09312426B2 Structure with a metal silicide transparent conductive electrode and a method of forming the structure 有权
标题翻译：具有金属硅化物透明导电电极的结构和形成该结构的方法
公开(公告)号：US09312426B2
公开(公告)日：2016-04-12
申请号：US13313101
申请日：2011-12-07
申请人： Jeffrey P. Gambino , Derrick Liu , Daniel S. Vanslette
发明人： Jeffrey P. Gambino , Derrick Liu , Daniel S. Vanslette
IPC分类号： H05K1/09 , B05D5/12 , B82Y99/00 , H01L31/18 , H01L31/0224 , H01L33/00 , H01L33/42 , H01L51/00 , B82Y10/00 , B82Y30/00 , H01B1/24 , H05K3/10
CPC分类号： H01L31/1884 , B82Y10/00 , B82Y30/00 , H01B1/24 , H01L31/022408 , H01L31/022425 , H01L31/022466 , H01L33/005 , H01L33/42 , H01L51/0021 , H05K3/105 , H05K2201/0108 , H05K2201/026 , H05K2203/1194 , Y02E10/50
摘要： Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure.
摘要翻译：公开了具有金属硅化物透明导电电极的结构的实施例，其具有商业上可行性，稳健且安全使用，并且因此最佳地结合到诸如平板显示器，触摸面板，太阳能电池，发光二极管 LED），有机光电子器件等。具体地，该结构可以包括衬底（例如，玻璃或塑料衬底）和该衬底上的透明导电膜。透明导电膜可以包括金属硅化物纳米线网络。例如，在一个实施例中，金属硅化物纳米线网络可以包括以无序布置融合在一起的多个金属硅化物纳米线，使得它们形成网状物。在另一个实施例中，金属硅化物纳米线网络可以包括图案化的多个金属硅化物纳米线，使得它们形成网格。这里还公开了用于形成这种结构的各种不同的方法实施例。

97. 发明授权

US09299837B2 Integrated circuit having MOSFET with embedded stressor and method to fabricate same 有权
标题翻译：具有嵌入式应力源的MOSFET的集成电路及其制造方法
公开(公告)号：US09299837B2
公开(公告)日：2016-03-29
申请号：US13900142
申请日：2013-05-22
申请人： GlobalFoundries U.S. 2 LLC
发明人： Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L29/786
CPC分类号： H01L29/7848 , H01L29/66636 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A method includes forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a channel region of a transistor; depositing a layer of crystalline dielectric material onto a surface of the substrate that is exposed within the recess; and depositing stressor material into the recess such that the layer of dielectric material is disposed between the stressor material and the surface of the substrate. A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate.
摘要翻译：一种方法包括在晶体半导体衬底中形成凹陷，所述凹槽设置在晶体管的沟道区的下方并围绕晶体管的沟道区; 在衬底的表面上沉积一层结晶介电材料，所述表面暴露在所述凹槽内; 以及将应力源材料沉积到所述凹部中，使得所述电介质材料层设置在所述应力材料和所述衬底的表面之间。结构包括设置在设置在结晶半导体衬底的表面上的BOX上的SOI层上的栅极堆叠或栅极堆叠前体。晶体管沟道设置在SOI层内。该结构还包括通道应力层，其至少部分地设置在衬底中的凹槽内并围绕通道设置，以及设置在应力层和衬底表面之间的结晶介电材料层。

98. 发明授权

US09299024B2 Method of answering questions and scoring answers using structured knowledge mined from a corpus of data 有权
标题翻译：使用从数据语料库挖掘的结构化知识回答问题和评分答案的方法
公开(公告)号：US09299024B2
公开(公告)日：2016-03-29
申请号：US13710708
申请日：2012-12-11
申请人： International Business Machines Corporation
发明人： Sugato Bagchi , David A. Ferrucci , Anthony T. Levas , Erik T. Mueller
IPC分类号： G06F17/00 , G06N5/02 , G06F17/30 , G06N5/04 , G06N99/00
CPC分类号： G06N5/02 , G06F17/30654 , G06N5/04 , G06N99/005
摘要： In a method of answering questions and scoring answers, a title and at least one topical field are identified for a document. A field name and field content associated with the topical field is identified, and a title-oriented document is created by combining the title, the field name, and the field content associated with the topical field. For each title-oriented document, a term in the title is matched to previously established categories to produce a title concept identifier. The topical field is synthesized to produce a field concept identifier and a field content concept identifier. A question is received. The question topic term and the question content identifier are used to identify at least one question-matching relation instance. The title concept identifier of each question-matching relation instance is identified as a candidate answer to the question. Each candidate answer and a corresponding answer score is output.
摘要翻译：在回答问题和评分答案的方法中，为文档识别标题和至少一个专题字段。识别与主题字段相关联的字段名称和字段内容，并通过组合标题，字段名称和与主题字段相关联的字段内容来创建面向标题的文档。对于每个面向标题的文档，标题中的术语与先前建立的类别相匹配，以产生标题概念标识符。合成局部场以产生场概念标识符和场内容概念识别符。收到一个问题。问题主题术语和问题内容标识符用于识别至少一个问题匹配关系实例。每个问题匹配关系实例的标题概念标识符被确定为该问题的候选答案。输出每个候选答案和相应的答案分数。

99. 发明授权

US09292576B2 Hypothesis-driven, real-time analysis of physiological data streams using textual representations 有权
标题翻译：假设驱动，使用文本表示的生理数据流的实时分析
公开(公告)号：US09292576B2
公开(公告)日：2016-03-22
申请号：US13570680
申请日：2012-08-09
申请人： Alain E. Biem , Timothy R. Dinger , Nagui Halim , Gang Luo , Daby M. Sow , Deepak S. Turaga
发明人： Alain E. Biem , Timothy R. Dinger , Nagui Halim , Gang Luo , Daby M. Sow , Deepak S. Turaga
IPC分类号： G06F17/30 , G06N5/02 , G06F19/00
CPC分类号： G06F19/324 , G06F17/30516 , G06F19/00 , G06N5/02 , G16H50/20
摘要： A method of analyzing physiological data streams. According to the method, physiological data is received into a computerized machine. The physiological data comprises numerical data and medical symptoms of a patient. Features are extracted from the physiological data based on development of the physiological data over a period of time. The features are converted into a textual representation using natural language generation. Input terms for an information retrieval system operating on the computerized machine are automatically generated based on the features. The input terms are input to the information retrieval system. A corpus of data is automatically searched to retrieve results to the input terms using the information retrieval system.
摘要翻译：分析生理数据流的方法。根据该方法，将生理数据接收到计算机化机器中。生理数据包括患者的数值数据和医学症状。基于一段时间内生理数据的发展，从生理数据中提取特征。使用自然语言生成将特征转换为文本表示。基于功能自动生成在计算机化机器上运行的信息检索系统的输入项。输入项输入到信息检索系统。使用信息检索系统自动搜索数据语料库以将结果检索到输入项。

100. 发明授权

US09274283B1 Silicon photonics alignment tolerant vertical grating couplers 有权
标题翻译：硅光子对准容限垂直光栅耦合器
公开(公告)号：US09274283B1
公开(公告)日：2016-03-01
申请号：US14501720
申请日：2014-09-30
申请人： International Business Machines Corporation
发明人： John J. Ellis-Monaghan , William M. J. Green , Jens Hofrichter , Marwan H. Khater , Jessie C. Rosenberg , Steven M. Shank
IPC分类号： G02B6/34 , G02B6/132 , G02B6/30 , G02B6/12
CPC分类号： G02B6/34 , G02B6/12002 , G02B6/132 , G02B6/30 , G02B2006/12107
摘要： Disclosed are optoelectronic integrated circuit structures that incorporate a first optical waveguide, having a semiconductor core, indirectly coupled to a grating coupler through a second optical waveguide, having a dielectric core, in order provide a relatively large alignment tolerance. The dielectric core can comprise multiple dielectric layers above one end of the semiconductor core and extending laterally over an isolation region adjacent to that end. The grating coupler can include dielectric fins above the isolation region. Alternatively, the grating coupler can include semiconductor fins within the isolation region. Also disclosed herein are methods of forming such optoelectronic integrated circuit structures that can be readily integrated with complementary metal oxide semiconductor (CMOS) device processing and germanium photodetector processing.
摘要翻译：公开了光电集成电路结构，其结合有第一光波导，其具有通过第二光波导间接耦合到光栅耦合器的半导体芯，其具有介电芯，以提供相对大的对准公差。电介质芯可以包括在半导体芯的一端上方的多个电介质层，并且横向延伸在与该端相邻的隔离区上。光栅耦合器可以包括隔离区上方的介质鳍片。或者，光栅耦合器可以包括隔离区域内的半导体鳍片。本文还公开了形成这样的光电子集成电路结构的方法，该结构可以容易地与互补金属氧化物半导体（CMOS）器件处理和锗光电检测器处理集成。

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