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91. 发明授权

US08605622B2 Route setup server, route setup method and route setup program 失效
标题翻译：路由设置服务器，路由设置方法和路由设置程序
公开(公告)号：US08605622B2
公开(公告)日：2013-12-10
申请号：US13176636
申请日：2011-07-05
申请人： Hideyuki Shimonishi
发明人： Hideyuki Shimonishi
IPC分类号： H04J1/16
CPC分类号： H04L45/54 , H04L45/02 , H04L45/38 , H04L45/42
摘要： A route setup server has a storage unit, an IP routing unit and a flow management unit. A routing determination table indicating a router node assigned to an IP router among the plurality of nodes is stored in the storage unit. The IP routing unit has a software-based IP routing module having a same function as an IP router with respect to each router node. The flow management unit refers to the routing determination table to check whether or not a requestor node of a route setup request corresponds to any router node. The IP routing unit performs packet IP routing by using the software-based IP routing module associated with the corresponding router node to update a header of the packet. After that, the requestor node of the route setup request is updated to a destination node designated by a destination MAC address of the packet. Such the processing is repeated and thus the communication route is determined.
摘要翻译：路由建立服务器具有存储单元，IP路由单元和流管理单元。指示分配给多个节点中的IP路由器的路由器节点的路由决定表存储在存储单元中。 IP路由单元具有与每个路由器节点相同的功能与IP路由器相同的基于软件的IP路由模块。流管理单元参照路由决定表，检查路由建立请求的请求方节点是否对应于任何路由器节点。 IP路由单元通过使用与相应路由器节点相关联的基于软件的IP路由模块来执行分组IP路由来更新分组的报头。之后，路由建立请求的请求者节点被更新到由分组的目的地MAC地址指定的目的地节点。这样的处理被重复，因此确定通信路由。

92. 发明授权

US08605524B2 Semiconductor device and semiconductor memory device 失效
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US08605524B2
公开(公告)日：2013-12-10
申请号：US13653265
申请日：2012-10-16
申请人： Elpida Memory, Inc.
发明人： Soichiro Yoshida
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/04 , G11C7/067 , G11C7/22 , G11C11/4076 , G11C11/4091
摘要： A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor.
摘要翻译：半导体器件包括存储单元，耦合到存储单元的第一位线，第二位线，包括第一和第二晶体管的第一读出放大器电路，第一晶体管包括耦合到第一位线的栅极，第一晶体管包括第一位线并且第二晶体管串联耦合在第二位线和第一电压线之间，温度检测电路被配置为检测半导体器件的温度，以及控制电路，被配置为接收温度检测电路的输出并提供控制信号到第二晶体管的栅极。

93. 发明授权

US08599327B2 Liquid crystal display apparatus and method for dust prevention of liquid crystal display apparatus 有权
标题翻译：液晶显示装置的防尘液晶显示装置及方法
公开(公告)号：US08599327B2
公开(公告)日：2013-12-03
申请号：US11640899
申请日：2006-12-19
申请人： Tomokazu Fujishima
发明人： Tomokazu Fujishima
IPC分类号： G02F1/1333 , G02F1/1345
CPC分类号： G02F1/133308 , G02F1/133608 , G02F2001/133311 , G02F2202/28
摘要： Disclosed is a liquid crystal display apparatus including a liquid crystal panel, and a backlight unit which is disposed on a back side of the liquid crystal panel, wherein the liquid crystal display apparatus further includes a dust preventing tape which is stuck to a region including at least a peripheral portion of a display surface of the liquid crystal panel and a side surface of the backlight unit in order to cover the region. A dust preventing method for a liquid crystal display apparatus is also disclosed.
摘要翻译：公开了一种液晶显示装置，包括液晶面板和设置在液晶面板背面的背光单元，其中液晶显示装置还包括防尘带，该防尘带粘附在包括至少液晶面板的显示面的周边部分和背光单元的侧面，以覆盖该区域。还公开了一种用于液晶显示装置的防尘方法。

94. 发明授权

US08598471B2 Electric storage device 有权
标题翻译：蓄电装置
公开(公告)号：US08598471B2
公开(公告)日：2013-12-03
申请号：US13336947
申请日：2011-12-23
申请人： Katsuhiko Okamoto , Shinsuke Yoshitake , Jun Nakamura , Masakazu Tsutsumi , Nobuyuki Naganawa
发明人： Katsuhiko Okamoto , Shinsuke Yoshitake , Jun Nakamura , Masakazu Tsutsumi , Nobuyuki Naganawa
IPC分类号： H01L23/48 , H01M2/02
CPC分类号： H01M2/06 , H01M2/04 , H01M2/30
摘要： There is provided an electric storage device having a novel fastening structure of a plastic member which can reduce cost with a simple configuration. An electric storage device according to this invention includes an electrode assembly, a case housing the electrode assembly, a plastic member arranged at an outer surface of the case, the plastic member having a joining surface facing the outer surface of the case, and an external terminal supported by the plastic member and electrically connected to the electrode assembly. The plastic member is a synthetic resin containing an inorganic fiber and is bonded to the outer surface of the case with the inorganic fiber exposed at the joining surface.
摘要翻译：提供一种具有塑料构件的新型紧固结构的蓄电装置，其可以以简单的构造降低成本。根据本发明的蓄电装置包括电极组件，容纳电极组件的壳体，布置在壳体的外表面处的塑料构件，塑料构件具有面向壳体的外表面的接合表面，以及外部端子由塑料构件支撑并电连接到电极组件。塑料构件是含有无机纤维的合成树脂，并且在接合表面露出无机纤维的情况下与外壳的外表面接合。

95. 发明授权

US08598459B2 Shielded cable 有权
标题翻译：屏蔽电缆
公开(公告)号：US08598459B2
公开(公告)日：2013-12-03
申请号：US12923406
申请日：2010-09-20
申请人： Hirotaka Eshima
发明人： Hirotaka Eshima
IPC分类号： H01B7/18
CPC分类号： H01B11/1821 , H01B11/1878
摘要： A shielded cable includes a core comprising an insulated wire including an inner conductor and an insulation layer formed on an outer periphery of the inner conductor, a shield layer formed on an outer periphery of the core, and a jacket layer formed on an outer periphery of the shield layer. The shield layer includes a stranded conductor shield layer including a stranded conductor spirally wound around the core, and the stranded conductor includes a plurality of conductor strands stranded together. The shield layer may further include a tinsel copper braided shield layer or a metal plated strand braided shield layer that is formed between the core and the stranded conductor shield layer.
摘要翻译：屏蔽电缆包括：芯，其包括绝缘电线，绝缘线包括内导体和形成在内导体的外周上的绝缘层，形成在芯的外周上的屏蔽层和形成在芯的外周上的护套层屏蔽层。屏蔽层包括绞合的导体屏蔽层，该绞合导体屏蔽层包括围绕芯部螺旋缠绕的绞合导体，并且绞合导体包括多个绞合在一起的导线。屏蔽层还可以包括形成在芯体和绞合导体屏蔽层之间的金属丝铜编织屏蔽层或金属电镀线编织屏蔽层。

96. 发明授权

US08592942B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US08592942B2
公开(公告)日：2013-11-26
申请号：US12320102
申请日：2009-01-16
申请人： Noriaki Kodama , Kenichi Hidaka , Hiroyuki Kobatake , Takuji Onuma
发明人： Noriaki Kodama , Kenichi Hidaka , Hiroyuki Kobatake , Takuji Onuma
IPC分类号： H01L27/11
CPC分类号： H01L27/112 , G11C17/16 , H01L27/11206
摘要： A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

97. 发明授权

US08582401B2 Library device including a tapered shape insertion release part, method of taking out data cartridge, and method of receiving the data cartridge 有权
标题翻译：包括锥形插入释放部件，取出数据盒的方法和接收数据盒的方法的库装置
公开(公告)号：US08582401B2
公开(公告)日：2013-11-12
申请号：US12733506
申请日：2008-09-22
申请人： Toshimitsu Kawasaki , Manabu Tsuchiya , Tadashi Kosugi
发明人： Toshimitsu Kawasaki , Manabu Tsuchiya , Tadashi Kosugi
IPC分类号： G11B21/08
CPC分类号： G11B15/6835 , G11B15/6885 , G11B17/225
摘要： A cell (300) includes a cartridge lock (306) at its opening for securing a data cartridge (100) in the cell by locking. A picker mechanism (500) includes a picker arm (521) and an ejection release part (522) for releasing locking realized by the cartridge lock (306). When the data cartridge (100) is to be inserted into the cell (300), the cartridge lock (306) is caused to retract as far as a position at which locking is released by a tapered surface (101) that is provided on the data cartridge (100); and when the data cartridge (100) is to be ejected from the cell (300), cartridge lock (306) is released by the ejection release part (522) at the same time that picker arm (521) engages engagement hole (102).
摘要翻译：电池（300）在其开口处包括盒锁（306），用于通过锁定将数据盒（100）固定在电池中。拾取机构（500）包括用于释放由盒锁（306）实现的锁定的拾取臂（521）和排出释放部（522）。当数据盒式磁盘（100）被插入单元（300）中时，使盒锁（306）缩回到通过设置在单元（300）上的锥形表面（101）释放锁定的位置数据盒（100）; 并且当数据盒式磁带（100）从单元（300）中被排出时，在该拾取臂（521）接合接合孔（102）的同时，通过喷射释放部分（522）释放盒锁（306）。

98. 发明授权

US08558169B2 Sample substrate for laser desorption ionization-mass spectrometry, and method and device both using the same for laser desorption ionization-mass spectrometry 失效
标题翻译：用于激光解吸电离质谱的样品衬底，以及用于激光解吸电离质谱法的方法和装置
公开(公告)号：US08558169B2
公开(公告)日：2013-10-15
申请号：US13388970
申请日：2010-07-29
申请人： Masaru Hori , Hiroaki Sato , Yasutake Toyoshima , Mineo Hiramatsu
发明人： Masaru Hori , Hiroaki Sato , Yasutake Toyoshima , Mineo Hiramatsu
IPC分类号： H01J49/00
CPC分类号： G01N27/622
摘要： An object of the present invention is to provide a sample substrate for laser desorption ionization mass spectrometry for LDI-MS which substrate enables mass spectrometric analysis of a sample correctly at high sensitivity without generating interference peaks upon irradiation of the sample to laser light and uniform application of the sample onto a base. Another object of the invention is to provide a mass spectrometer (device) employing the sample substrate.In the sample substrate for laser desorption ionization mass spectrometry, the sample substrate is formed of a base and carbon nanowalls having wall surfaces onto which a sample to undergo mass spectrometry is applied, wherein the carbon nanowalls are formed on the base so as to stand on the base. The surfaces of carbon nanowalls serve as an ionization medium and hydrophilized. By use of the sample substrate, mass spectrometry of a sample having a wide range (high to low) molecular weight can be reliably performed at high precision and sensitivity.
摘要翻译：本发明的目的是提供一种用于LDI-MS的激光解吸电离质谱的样品基片，该基片能够以高灵敏度正确地对样品进行质谱分析，而不会在将样品照射到激光上并产生均匀的应用时产生干涉峰的样品到基底上。本发明的另一个目的是提供一种采用样品基质的质谱仪（装置）。在用于激光解吸电离质谱的样品衬底中，样品衬底由具有壁表面的基底和碳纳米壁形成，其上应用要进行质谱的样品，其中碳纳米壁形成在基底上以便立在的基地。碳纳米壁的表面用作电离介质并亲水化。通过使用样品基板，可以以高精度和灵敏度可靠地进行具有宽范围（高低分子量）的样品的质谱分析。

99. 发明授权

US08539203B2 Multi-thread processor selecting threads on different schedule pattern for interrupt processing and normal operation 有权
标题翻译：多线程处理器在不同的调度模式下选择线程进行中断处理和正常运行
公开(公告)号：US08539203B2
公开(公告)日：2013-09-17
申请号：US12585737
申请日：2009-09-23
申请人： Koji Adachi , Toshiyuki Matsunaga
发明人： Koji Adachi , Toshiyuki Matsunaga
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3867 , G06F9/4893 , Y02D10/24
摘要： In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the thread scheduler selects the second schedule.
摘要翻译：在一个示例性方面，本发明提供一种多线程处理器，包括多个硬件线程，每个硬件线程生成独立的指令流，线程调度器，其根据第一或第二调度输出线程选择信号，线程选择指定要在所述多个硬件线程中的下一个执行周期中执行的硬件线程;第一选择器，其根据所述线程选择信号选择所述多个硬件线程中的一个，并输出由所选择的硬件线程生成的指令;以及执行从第一选择器输出的指令的执行管线，其中当所述多线程处理器处于第一状态时，所述线程调度器选择所述第一调度，并且当所述多线程处理器处于第二状态时，所述线程调度器选择第二个时间表。

100. 发明授权

US08525771B2 Image display apparatus and method of adjusting clock phase using delay evaluation signal 有权
标题翻译：使用延迟评估信号调整时钟相位的图像显示装置及方法
公开(公告)号：US08525771B2
公开(公告)日：2013-09-03
申请号：US12662360
申请日：2010-04-13
申请人： Toshiyuki Kawana , Michiya Nishida
发明人： Toshiyuki Kawana , Michiya Nishida
IPC分类号： G09G3/36
CPC分类号： G09G5/008 , H03L7/08 , H03L7/18
摘要： An image display apparatus includes a controller for dividing at least a portion of an image displayed based on a digital video signal, into a plurality of image areas defined by display lines, and establishing different delays for the divided image areas, a clock adjuster generating a clock in synchronism with the dot clock, delaying a phase of the clock according to the delays established by the controller, for the respective divided image areas, and outputting the delayed clock as the reproduced dot clock, and a delay evaluating unit converting differential data between adjacent signal levels into absolute values and accumulatively adding the absolute values based on the reproduced dot clock output from the clock adjuster, with respect to the display lines which define the divided image areas, thereby producing accumulated sums. The controller judges the delay established for the divided area with the maximum accumulated sum, as optimum.
摘要翻译：图像显示装置包括：控制器，用于将基于数字视频信号显示的图像的至少一部分分割成由显示行定义的多个图像区域，并为分割图像区域建立不同的延迟;时钟调节器，时钟与点时钟同步，根据由控制器为各个分割图像区域建立的延迟延迟时钟的相位，并将延迟时钟作为再现点时钟输出，延迟评估单元将差分数据转换为相对于定义分割图像区域的显示线，基于从时钟调整器输出的再现点时钟累积地添加绝对值，从而产生累积和。控制器以最大累积和确定分割区域的最大延迟。

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