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1. 发明授权

US12028033B2 Filter circuitry using active inductor 有权
公开(公告)号：US12028033B2
公开(公告)日：2024-07-02
申请号：US17926083
申请日：2020-05-20
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Ufuk Özdemir , Peter Caputa , Kirill Kozmin
IPC分类号： H03H11/04 , H03D7/14 , H03L7/08 , H03M1/12 , H03M1/66
CPC分类号： H03H11/04 , H03D7/1491 , H03L7/08 , H03M1/12 , H03M1/66
摘要： A filter circuitry (200) using an active inductor is disclosed. The filter circuitry (200) has a first terminal (In1/Out1) and a second terminal (In2/Out2). The filter circuitry (200) comprises a first transistor (M1) and a second transistor (M2). The filter circuitry (200) further comprises a first switch (S1), a second switch (S2), a first capacitor (C1), a second capacitor (C2) and a resistor (R). The first and second transistors (M1/M2) together with the resistor (R) and the first and second switches (S1/S2) are connected in a current mirror topology. The first and second capacitors (C1/C2) are connected at the first and second terminals of the filter circuitry (200) respectively. The filter circuitry (200) is configurable to either have the first terminal (In1/Out1) as input and the second terminal (In2/Out2) as output or have the first terminal (In1/Out1) as output and the second terminal (In2/Out2) as input by changing on-off states of the first and second switches. The transistors are interconnected in a current-mirror fashion. Depending on the switch position one of the transistors also acts as part of an active inductor such that the circuit functions as a low pass filter with a complex pole pair and a real pole. Depending on the switch position the LPF allows signal flow in either direction. For use in a TDD environment in combination with a passive mixer (420).

2. 发明授权

US12021312B2 Optically synchronized phased array 有权
公开(公告)号：US12021312B2
公开(公告)日：2024-06-25
申请号：US17378483
申请日：2021-07-16
申请人： California Institute of Technology
发明人： Matan Gal , Craig E. Ives , Armina Khakpour , Seyed Ali Hajimiri
IPC分类号： H01Q3/34 , H01L31/103 , H01Q1/22 , H03F3/195 , H03L7/08
CPC分类号： H01Q3/34 , H01L31/103 , H01Q1/2283 , H03F3/195 , H03L7/08 , H03F2200/451
摘要： Disclosed herein is a phased antenna array which is configured to provide a signal through multiple antennas. The phased antenna array may include a plurality of sub-arrays. Each sub-array may include a complete and functional optically synchronized integrated circuit including an integrated photo diode. Advantageously, integrating the photo diode into the integrated circuit may reduce the size of the sub-array and decrease the length the high frequency timing signal is passed.

3. 发明公开

US20240204755A1 Adaptive Clock Generator Circuit 审中-公开
公开(公告)号：US20240204755A1
公开(公告)日：2024-06-20
申请号：US18067624
申请日：2022-12-16
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Diljith THODI , Saikiran KURBA , Uttam AGARWAL
IPC分类号： H03K3/012 , G06F1/08 , G06F1/12 , H03L7/08
CPC分类号： H03K3/012 , G06F1/08 , G06F1/12 , H03L7/08
摘要： A circuit includes: digital circuits having respective clock inputs; and adaptive clock generator circuitry having clock outputs. Each respective clock input is coupled to one of the generator clock outputs. The adaptive clock generator circuitry includes: a processor having an input interface and an output interface; and clock generator resources having a control input, a root clock input and resource clock outputs. The processor is configured to provide resource configuration parameters at the output interface in response to clock settings received at the input interface and target settings. The control input is coupled to the output interface. Each resource clock output of the resource clock outputs is coupled a respective generator clock output of the generator clock outputs. The clock generator resources are configured to provide a respective clock signal at each of the resource clock outputs in response to the resource configuration parameters received at the control input.

4. 发明授权

US11996703B2 Wireless device 有权
公开(公告)号：US11996703B2
公开(公告)日：2024-05-28
申请号：US17191124
申请日：2021-03-03
申请人： CANON KABUSHIKI KAISHA
发明人： Yuki Shoji
IPC分类号： H02P23/06 , H02J50/12 , H02M1/08 , H02P7/03 , H02P29/68 , H03L7/08
CPC分类号： H02J50/12 , H02M1/083 , H02P7/04 , H03L7/08
摘要： A wireless device includes a power transmission coil configured to transmit power wirelessly, a power reception coil configured to receive the power wirelessly, a switch circuit configured to apply a voltage to the power transmission coil based on a first switching signal, and a rectification circuit configured to rectify a voltage output from the power reception coil based on a second switching signal and apply the rectified voltage to a load, wherein the switch circuit and the rectification circuit each include a plurality of bidirectional switches.

5. 发明授权

US11923854B2 Logic circuit 有权
公开(公告)号：US11923854B2
公开(公告)日：2024-03-05
申请号：US17718350
申请日：2022-04-12
申请人： CANON KABUSHIKI KAISHA
发明人： Kohichi Nakamura , Yasuhiro Oguro
IPC分类号： H03K3/037 , G06T7/55 , H04N25/71 , H03L7/08 , H03M9/00
CPC分类号： H03K3/037 , G06T7/55 , H04N25/745 , G06T2207/30252 , H03L7/08 , H03M9/00
摘要： Provided is a logic circuit including a first circuit including a static D flip-flop and a second circuit including a dynamic D flip-flop. The first circuit receives a clock signal and a first reset signal. The first circuit outputs a second reset signal generated by synchronizing the first reset signal with the clock signal. The second circuit receives the clock signal and a signal based on the second reset signal.

6. 发明授权

US11843251B2 Controller circuit for photovoltaic sub-module 有权
公开(公告)号：US11843251B2
公开(公告)日：2023-12-12
申请号：US17512459
申请日：2021-10-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Richard Hester , Timothy Patrick Pauletti , Suheng Chen , Amneh Mohammed Akour , Nat Maruthachalam Natarajan , Jayanth Rangaraju
IPC分类号： H02J3/38 , H03L7/08
CPC分类号： H02J3/381 , H02J2300/26 , H03L7/08
摘要： A controller circuit for a PV sub-module includes a power harvest controller circuit, a voltage limit controller circuit, a power mode control circuit, a multiplexer circuit, and a switching converter circuit. The power harvest controller circuit, including a first PV voltage input, a ceiling reference input, a floor reference input, and a first gate control output. The voltage limit controller circuit, including a first output voltage feedback input, a pulse width reference input, and a second gate control output. The power mode control circuit, including a second output voltage feedback input, a mode reference input, and a mode selection output. The multiplexer circuit, including a first gate control input, a second gate control input, a mode selection input, and a third gate control output. The switching converter circuit, including a second PV voltage input, a third gate control input, and a DC voltage output.

7. 发明公开

US20230361762A1 SYSTEM FOR SIGNAL PROPAGATION AND METHOD OF OPERATING THE SAME 审中-公开
公开(公告)号：US20230361762A1
公开(公告)日：2023-11-09
申请号：US18352286
申请日：2023-07-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： RUEY-BIN SHEEN , TSUNG-HSIEN TSAI , CHIH-HSIEN CHANG
IPC分类号： H03K5/01 , H03L7/08
CPC分类号： H03K5/01 , H03L7/08
摘要： An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.

8. 发明授权

US11808798B2 Jitter noise detector 有权
公开(公告)号：US11808798B2
公开(公告)日：2023-11-07
申请号：US17972475
申请日：2022-10-24
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tien-Chien Huang
IPC分类号： G01R29/26 , H03L7/08 , H03L7/07 , H03K19/0185 , G01R31/317 , G01R29/027
CPC分类号： G01R29/26 , G01R31/31709 , H03K19/01855 , H03L7/07 , H03L7/08 , G01R29/0276
摘要： A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

9. 发明授权

US11777310B2 Virtual inertia estimation for black-start using Tower of Hanoi (ToH) for emerging electricity distribution networks 有权
公开(公告)号：US11777310B2
公开(公告)日：2023-10-03
申请号：US17585072
申请日：2022-01-26
申请人： QATAR UNIVERSITY
发明人： Ahmed Massoud , Omar Ellabban , Abdulrahman Alassi
IPC分类号： G05B15/02 , H02J3/00 , H03L7/08
CPC分类号： H02J3/001 , G05B15/02 , H03L7/08
摘要： A method for managing a microgrid network under a blackout condition. The method may include partitioning the microgrid network into a plurality of clusters. The method may also include determining a virtual inertia value for each of the plurality of clusters. The method may further include classifying the plurality of clusters based on corresponding virtual inertia values. In addition, the method may include performing a black-start operation by employing a Tower of Hanoi concept to restore power to the microgrid network. According to certain embodiments, performance of the black-start operation may take into account the virtual inertial values.

10. 发明授权

US11757609B2 Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence 有权
公开(公告)号：US11757609B2
公开(公告)日：2023-09-12
申请号：US17324025
申请日：2021-05-18
申请人： Marvell Asia Pte, Ltd.
发明人： Scott E. Meninger
IPC分类号： H04L7/00 , H03L7/197 , G06F1/06 , H03L7/00 , H03L7/08 , H04L27/227 , H03M9/00 , G06F1/10 , H03L7/23 , H04L1/00 , H04J3/06
CPC分类号： H04L7/0008 , G06F1/06 , H03L7/00 , H03L7/08 , H03L7/1976 , H03L7/23 , H04L1/0065 , H04L27/2272 , G06F1/10 , H03M9/00 , H04J3/0685
摘要： A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

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