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91. 发明申请

US20160322325A1 COUPLING OF SIDE SURFACE CONTACTS TO A CIRCUIT PLATFORM 有权
标题翻译：与电路平台相连接的表面接触
公开(公告)号：US20160322325A1
公开(公告)日：2016-11-03
申请号：US14698684
申请日：2015-04-28
申请人： INVENSAS CORPORATION
发明人： Reynaldo CO , Willmar SUBIDO , Hoang NGUYEN , Marjorie CARA , Wael ZOHNI , Christopher W. LATTIN
IPC分类号： H01L23/00 , B81C1/00 , B23K20/00 , B81B7/00
CPC分类号： H01L24/49 , B81B7/007 , B81B7/0074 , B81B2207/05 , B81C1/00301 , H01L24/48 , H01L24/85 , H01L2224/16225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/4903 , H01L2224/85045 , H01L2224/85203 , H01L2924/00014 , H01L2924/1461 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599
摘要： An apparatus relates generally to a microelectromechanical system component. In such an apparatus, the microelectromechanical system component has a lower surface, an upper surface, first side surfaces, and second side surfaces. Surface area of the first side surfaces is greater than surface area of the second side surfaces. The microelectromechanical system component has a plurality of wire bond wires attached to and extending away from a first side surface of the first side surfaces. The wire bond wires are self-supporting and cantilevered with respect to the first side surface of the first side surfaces.
摘要翻译：一种装置一般涉及微机电系统部件。在这种装置中，微机电系统部件具有下表面，上表面，第一侧表面和第二侧表面。第一侧面的表面积大于第二侧面的表面积。微电子机械系统部件具有多个连接到第一侧表面的第一侧表面并且远离第一侧表面的线接合线。线接合线相对于第一侧表面的第一侧表面是自支撑的和悬臂的。

92. 发明申请

US20160293556A1 WARPAGE REDUCTION IN STRUCTURES WITH ELECTRICAL CIRCUITRY 有权
标题翻译：电路结构中的波纹减少
公开(公告)号：US20160293556A1
公开(公告)日：2016-10-06
申请号：US15181861
申请日：2016-06-14
申请人： Invensas Corporation
发明人： Cyprian Emeka UZOH
IPC分类号： H01L23/00 , H01L21/66 , H01L21/78 , H01L21/3205
CPC分类号： H01L23/562 , H01L21/32051 , H01L21/78 , H01L22/12 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2224/0345 , H01L2224/05124 , H01L2224/05181 , H01L2924/12042 , H01L2924/00
摘要： To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.
摘要翻译：为了减少晶片的至少一个区域中的翘曲，形成应力/翘曲管理层（810）以使现有翘曲的方向超平衡并改变。例如，如果该地区的中部相对于该地区的边界膨胀，该区域的中部可能会向下膨胀，反之亦然。然后处理压力/翘曲管理层以减少过度平衡。例如，应力/管理层可以在选定位置从晶片剥离，或者可以在层中形成凹陷，或者可以在该层中引起相变。在其它实施例中，该层是钽 - 铝，其可能或可能不会使翘曲过度平衡; 这一层被认为是由于结晶相依赖的应力而减少翘曲，其动态地适应温度变化，以减少翘曲（可能通过热循环保持晶片平坦）。还提供其他功能。

93. 发明授权

US09461196B2 Non-crystalline inorganic light emitting diode 有权
公开(公告)号：US09461196B2
公开(公告)日：2016-10-04
申请号：US14605550
申请日：2015-01-26
申请人： Invensas Corporation
发明人： Ilyas Mohammed , Liang Wang
IPC分类号： H01L33/10 , H01L33/00 , H01L33/18 , H01L33/16 , H05B33/14 , H05B33/22 , H01L33/14 , H01L33/36 , H01L33/48
CPC分类号： H01L33/0012 , H01L33/0095 , H01L33/14 , H01L33/16 , H01L33/18 , H01L33/36 , H01L33/486 , H01L2933/0016 , H01L2933/0033 , H05B33/14 , H05B33/22
摘要： Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier.

94. 发明授权

US09460758B2 Single package dual channel memory with co-support 有权
公开(公告)号：US09460758B2
公开(公告)日：2016-10-04
申请号：US14753607
申请日：2015-06-29
申请人： Invensas Corporation
发明人： Richard Dewitt Crisp , Yong Chen , Belgacem Haba , Wael Zohni , Zhuowen Sun
IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C8/00 , G11C8/16 , G11C8/18 , H01L23/00 , H01L25/065 , G11C5/04 , G11C8/12 , G11C11/408 , H01L23/538 , H01L25/10
CPC分类号： G11C5/025 , G11C5/04 , G11C5/063 , G11C8/12 , G11C11/408 , H01L23/5386 , H01L23/5389 , H01L24/00 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/10253 , H01L2924/10329 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

95. 发明申请

US20160284672A1 THERMAL VIAS DISPOSED IN A SUBSTRATE PROXIMATE TO A WELL THEREOF 有权
标题翻译：在基材中处理的热叶可以很好地替代
公开(公告)号：US20160284672A1
公开(公告)日：2016-09-29
申请号：US15174338
申请日：2016-06-06
申请人： Invensas Corporation
发明人： Rajesh Katkar , Arkalgud R. Sitaram , Cyprian Emeka Uzoh
IPC分类号： H01L25/065 , H01L23/367
CPC分类号： H01L25/0657 , H01L21/30604 , H01L21/308 , H01L21/31105 , H01L21/76897 , H01L21/76898 , H01L23/3675 , H01L23/3677 , H01L23/42 , H01L23/481 , H01L23/5386 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/06541 , H01L2225/06589 , H01L2924/15311 , H01L2924/16152 , H01L2924/00
摘要： An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.
摘要翻译：装置一般涉及三维堆叠集成电路。在这种装置中，三维堆叠集成电路具有至少第一管芯和第二管芯，使用管芯到管芯互连彼此互连。第一管芯的衬底具有至少一个热通孔结构，其从衬底的下表面朝向衬底的阱延伸，而不延伸到阱并且不延伸通过衬底。所述至少一个热通孔结构的第一端至少足够靠近所述衬底的阱，用于将热量传导出来。衬底具有从衬底的下表面延伸到衬底的上表面的至少一个穿过衬底通孔结构。所述至少一个热通孔结构的第二端与所述第二管芯的至少一个通孔通孔结构耦合以进行导热。

97. 发明申请

US20160260687A1 EMBEDDED GRAPHITE HEAT SPREADER FOR 3DIC 有权
标题翻译：嵌入式石墨加热器3DIC
公开(公告)号：US20160260687A1
公开(公告)日：2016-09-08
申请号：US14639942
申请日：2015-03-05
申请人： Invensas Corporation
发明人： Guilian Gao , Charles G. Woychik , Cyprian Emeka Uzoh , Liang Wang
IPC分类号： H01L25/065 , H01L23/373 , H01L23/00 , H01L25/00 , H01L23/367
CPC分类号： H01L25/0657 , H01L23/36 , H01L23/367 , H01L23/3675 , H01L23/373 , H01L24/00 , H01L24/11 , H01L24/17 , H01L24/27 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/11334 , H01L2224/16057 , H01L2224/16145 , H01L2224/2761 , H01L2224/32245 , H01L2224/81815 , H01L2224/838 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/01006 , H01L2924/10253
摘要： A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.
摘要翻译：介绍了一种具有热控制功能的设备。在一些实施例中，该装置包括位于堆叠中的多个管芯，每个管芯包括芯片，通过芯片的厚度相互连接，导电组合物的金属特征连接到芯片的底侧上的互连件和粘合剂或底部填充层。至少一个热传导层，其可以是热解石墨层，由碳纳米管形成的层或石墨烯层，被耦合在多个管芯中的一个的顶侧和邻接的管芯的底侧之间堆栈散热器可以耦合到导热层。

98. 发明申请

US20160254205A1 DEVICE AND METHOD FOR LOCALIZED UNDERFILL 有权
标题翻译：用于本地化的设备和方法
公开(公告)号：US20160254205A1
公开(公告)日：2016-09-01
申请号：US15151176
申请日：2016-05-10
申请人： Invensas Corporation
发明人： Liang WANG , Rajesh KATKAR , Charles G. WOYCHIK , Cyprian Emeka UZOH
IPC分类号： H01L23/31 , H01L25/00 , H01L21/48 , H01L21/52 , H01L21/54 , H01L25/065 , H01L23/498
CPC分类号： H01L23/3178 , H01L21/4853 , H01L21/52 , H01L21/54 , H01L21/563 , H01L23/13 , H01L23/3157 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/0655 , H01L25/50 , H01L2224/131 , H01L2224/16227 , H01L2224/26175 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2225/06517 , H01L2225/06555 , H01L2225/06593 , H01L2924/15153 , H01L2924/15156 , H01L2924/014
摘要： A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts and a plurality of cavities separated by a plurality of mesas. The plurality of dies is mounted to the substrate using the plurality of contacts. The underfill material is located between the substrate and the dies. The underfill material is localized into a plurality of regions using the mesas. Each of the contacts is located in a respective one of the cavities. In some embodiments, the substrate further includes a plurality of channels interconnecting the cavities. In some embodiments, the substrate further includes a plurality of intra-cavity mesas for further localizing the underfill material. In some embodiments, outer edges of a first one of the dies rest on first mesas located on edges of a first one of the cavities.
摘要翻译：用于定位底部填充物的装置和方法包括基底，多个模具和底部填充材料。衬底包括多个触点和由多个台面隔开的多个空腔。使用多个触点将多个模具安装到基板。底部填充材料位于基底和模具之间。使用台面将底部填充材料定位到多个区域中。每个触点位于相应的一个空腔中。在一些实施例中，衬底还包括互连空腔的多个通道。在一些实施例中，衬底还包括用于进一步定位底部填充材料的多个腔内台面。在一些实施例中，第一模具的外边缘位于位于第一空腔的边缘上的第一台面上。

99. 发明授权

US09433093B2 High strength through-substrate vias 有权
标题翻译：高强度通衬底通孔
公开(公告)号：US09433093B2
公开(公告)日：2016-08-30
申请号：US14337196
申请日：2014-07-21
申请人： INVENSAS CORPORATION
发明人： Cyprian Emeka Uzoh
IPC分类号： H05K1/11 , H05K3/42 , H01L23/498 , H05K1/03 , H05K1/09 , H01L23/14
CPC分类号： H05K1/115 , H01L23/14 , H01L23/49827 , H01L23/49866 , H01L2924/0002 , H05K1/03 , H05K1/09 , H05K3/42 , H05K2201/0141 , H05K2201/0175 , H05K2201/09509 , H05K2201/10378 , H05K2203/025 , H05K2203/1105 , Y10T29/49165 , H01L2924/00
摘要： A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.
摘要翻译：组件包括具有第一和第二间隔开并平行表面的支撑结构以及沿第一和第二表面之间的方向延伸的多个导电元件。每个导电元件包含选自铜，铝，镍和铬的布线金属的合金和选自由镓，锗，铟，硒，锡，硫，银，磷和铋。该合金具有随导电元件的至少一个方向上的距离而变化的组成。添加剂的浓度小于或等于导电元件的总原子质量的5％，并且导电元件的电阻率在2.5至30微欧姆厘米之间。

100. 发明授权

US09418924B2 Stacked die integrated circuit 有权
标题翻译：堆叠模具集成电路
公开(公告)号：US09418924B2
公开(公告)日：2016-08-16
申请号：US14220912
申请日：2014-03-20
申请人： Invensas Corporation
发明人： Charles G. Woychik , Cyprian Emeka Uzoh , Ron Zhang , Daniel Buckminster , Guilian Gao
IPC分类号： H01L21/30 , H01L23/498 , H01L21/52 , H01L21/78 , H01L23/48 , H01L23/00 , H01L25/065 , H01L21/768 , H01L21/304 , H01L23/13
CPC分类号： H01L25/0657 , H01L21/304 , H01L21/4853 , H01L21/486 , H01L21/52 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L23/13 , H01L23/3114 , H01L23/481 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/85 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/1703 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06548 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2924/00014 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/16235 , H01L2924/16251 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2224/83 , H01L2224/81 , H01L2924/014 , H01L2924/0105 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.
摘要翻译：装置一般涉及集成电路封装。在这种装置中，封装衬底具有从封装衬底的下表面延伸到封装衬底的上表面的第一多个通孔结构。模具具有延伸到模具的下表面的第二多个通孔结构。模具的下表面在集成电路封装中面向封装衬底的上表面。封装基板不包括再分布层。管芯和封装衬底彼此耦合。

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