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1. 发明授权

US09349707B1 Contact arrangements for stackable microelectronic package structures with multiple ranks 有权
标题翻译：具有多个级别的可堆叠微电子封装结构的接触布置
公开(公告)号：US09349707B1
公开(公告)日：2016-05-24
申请号：US14609896
申请日：2015-01-30
申请人： Invensas Corporation
发明人： Zhuowen Sun , Yong Chen , Kyong-Mo Bang
IPC分类号： H01L23/02 , H01L25/065 , H01L25/00 , H01L23/00 , H01L23/498 , H01L21/48
CPC分类号： H01L25/0652 , H01L21/486 , H01L23/13 , H01L23/34 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/11 , H01L24/17 , H01L24/43 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L25/50 , H01L2224/13023 , H01L2224/13025 , H01L2224/16057 , H01L2224/16137 , H01L2224/16146 , H01L2224/16165 , H01L2224/16235 , H01L2224/32145 , H01L2224/4502 , H01L2224/48138 , H01L2224/48148 , H01L2224/48165 , H01L2224/48235 , H01L2224/4824 , H01L2224/49174 , H01L2224/49177 , H01L2224/73265 , H01L2924/00014 , H01L2924/1434 , H01L2924/1511 , H01L2924/152 , H01L2924/15311 , H01L2924/1533 , H01L2924/3701 , H01L2224/45099
摘要： An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact arrangements are disposed on a surface of the first substrate, including: first contacts disposed as a ring to provide a first array of the contact arrangements on such surface; and second contacts disposed interior to the ring of the first contacts to provide a second array of the contact arrangements on the first surface. The first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies. The second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies. The first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.
摘要翻译：装置一般涉及微电子组件。在该装置中，第一基板和第二基板各自具有相对的表面。接触装置设置在第一基板的表面上，包括：作为环设置的第一触点，以在该表面上提供接触装置的第一阵列; 以及第二触点，其设置在第一触头的环的内部，以在第一表面上提供接触装置的第二阵列。第一触点和第二触点用于与第一微电子管芯和第二微电子管芯互连。第二微电子管芯以与第一微电子管芯相同的封装设置在第一微电子管芯的下方。第一微电子管芯和第二微电子管芯包括至少两个等级，用于共同共享第一微触点和第一微电子管芯与第二微电子管芯之间的第二触点。

2. 发明授权

US09337170B1 Contact arrangements for stackable microelectronic package structures 有权
标题翻译：可堆叠微电子封装结构的接触布置
公开(公告)号：US09337170B1
公开(公告)日：2016-05-10
申请号：US14609878
申请日：2015-01-30
申请人： Invensas Corporation
发明人： Zhuowen Sun , Yong Chen , Kyong-Mo Bang
IPC分类号： H01L29/40 , H01L25/065 , H01L23/498 , H01L25/00 , H01L21/48
CPC分类号： H01L25/0652 , H01L23/13 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/06135 , H01L2224/06136 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/1703 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/14 , H01L2924/1434 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/16152 , H01L2924/16251 , H01L2924/181 , H01L2924/014 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An apparatus relates generally to a microelectronic assembly. In such an apparatus, a contact arrangements are disposed on a first surface of a first substrate, including first contacts disposed as a first ring array; second contacts disposed interior to the first contacts as a second ring array; third contacts disposed interior to the second contacts as a third ring array; and fourth contacts disposed interior to the third contacts on the first surface as an innermost array. The first ring array, the second ring array, and the third ring array are concentric rings with the innermost array in a central region of the concentric rings. The first contacts and the fourth contacts are for interconnection with first microelectronic dies. The second contacts and the third contacts are for interconnection with second microelectronic dies.
摘要翻译：装置一般涉及微电子组件。在这种装置中，接触装置设置在第一基板的第一表面上，包括设置为第一环阵列的第一触点; 第二触点设置在第一触点内部作为第二环阵列; 设置在第二触点内部的第三触点作为第三环阵列; 以及第四触点，其设置在第一表面上的作为最内侧阵列的第三触点的内部。第一环阵列，第二环阵列和第三环阵列是在同心环的中心区域中具有最内阵列的同心环。第一触点和第四触点用于与第一微电子模具互连。第二触点和第三触点用于与第二微电子管芯互连。

3. 发明授权

US09241420B2 In-package fly-by signaling 有权
标题翻译：包装内飞行信号
公开(公告)号：US09241420B2
公开(公告)日：2016-01-19
申请号：US14275098
申请日：2014-05-12
申请人： Invensas Corporation
发明人： Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Yong Chen
IPC分类号： H01L23/48 , H01L23/34 , H01L21/70 , H05K7/14 , H01L23/13 , H01L25/065 , G11C5/06 , H01L23/498 , H01L23/31
CPC分类号： H05K7/1459 , G11C5/063 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L25/0655 , H01L2224/4824 , H01L2924/15311
摘要： In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region.
摘要翻译：可以在具有在封装衬底上的地址线的多芯片微电子封装中提供封装内的飞越信号，该封装衬底被配置为将地址信息传送到具有来自封装端子的第一延迟的衬底上的第一连接区域，并且地址线路被配置为将地址信息超出第一连接区域至少至少具有来自大于第一延迟的端子的具有第二延迟的第二连接区域。第一微电子元件（例如，半导体芯片）的地址输入可以与第一连接区域处的每个地址线耦合，并且第二微电子元件的地址输入可以在第二连接区域与每个地址线耦合。

4. 发明申请

US20140268537A1 IN-PACKAGE FLY-BY SIGNALING 有权
标题翻译： IN-PACKAGE FLY-BY信号
公开(公告)号：US20140268537A1
公开(公告)日：2014-09-18
申请号：US14275098
申请日：2014-05-12
申请人： INVENSAS CORPORATION
发明人： Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Yong Chen
IPC分类号： H05K7/14
CPC分类号： H05K7/1459 , G11C5/063 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L25/0655 , H01L2224/4824 , H01L2924/15311
摘要： In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region.
摘要翻译：可以在具有在封装衬底上的地址线的多芯片微电子封装中提供封装内的飞越信号，该封装衬底被配置为将地址信息传送到具有来自封装端子的第一延迟的衬底上的第一连接区域，并且地址线路被配置为将地址信息超出第一连接区域至少至少具有来自大于第一延迟的端子的具有第二延迟的第二连接区域。第一微电子元件（例如，半导体芯片）的地址输入可以与第一连接区域处的每个地址线耦合，并且第二微电子元件的地址输入可以在第二连接区域与每个地址线耦合。

5. 发明授权

US09460758B2 Single package dual channel memory with co-support 有权
公开(公告)号：US09460758B2
公开(公告)日：2016-10-04
申请号：US14753607
申请日：2015-06-29
申请人： Invensas Corporation
发明人： Richard Dewitt Crisp , Yong Chen , Belgacem Haba , Wael Zohni , Zhuowen Sun
IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C8/00 , G11C8/16 , G11C8/18 , H01L23/00 , H01L25/065 , G11C5/04 , G11C8/12 , G11C11/408 , H01L23/538 , H01L25/10
CPC分类号： G11C5/025 , G11C5/04 , G11C5/063 , G11C8/12 , G11C11/408 , H01L23/5386 , H01L23/5389 , H01L24/00 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/10253 , H01L2924/10329 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

6. 发明申请

US20160093563A1 BGA BALLOUT PARTITION TECHNIQUES FOR SIMPLIFIED LAYOUT IN MOTHERBOARD WITH MULTIPLE POWER SUPPLY RAIL 有权
标题翻译： BGA BALLOUT分段技术，用于多台电源轨道车载板上的简化布局
公开(公告)号：US20160093563A1
公开(公告)日：2016-03-31
申请号：US14497825
申请日：2014-09-26
申请人： INVENSAS CORPORATION
发明人： Yong Chen , Zhuowen Sun , Kyong-Mo Bang
IPC分类号： H01L23/498 , H05K1/02
CPC分类号： H01L23/49816 , H01L23/49822 , H01L23/50 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2924/0002 , H01L2924/15192 , H01L2924/181 , H05K1/0262 , H05K2201/093 , H05K2201/09309 , H05K2201/09336 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.
摘要翻译：微电子封装可以包括衬底和微电子元件。衬底可以包括在衬底的表面处的区域阵列中至少包括第一电源端子和其他端子的端子。基板还可以包括电耦合到第一电源端子的功率平面元件。区域阵列可以具有周边边缘和在平行于表面的方向上从周边边缘向内延伸的端子之间的连续间隙。间隙的相对侧上的端子可以彼此间隔开至少1.5倍的端子的最小间距。功率平面元件可以在间隙内从至少外围边缘至少延伸到第一电源端子。每个第一电源端子可以通过两个或更多其它端子与外围边缘分离。

7. 发明申请

US20160093340A1 COMPACT MICROELECTRONIC ASSEMBLY HAVING REDUCED SPACING BETWEEN CONTROLLER AND MEMORY PACKAGES 有权
标题翻译：具有控制器和存储器封装之间的减少间隔的紧凑型微电子组件
公开(公告)号：US20160093340A1
公开(公告)日：2016-03-31
申请号：US14496159
申请日：2014-09-25
申请人： Invensas Corporation
发明人： Zhuowen Sun , Yong Chen
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C5/063 , G11C5/025 , H01L24/00
摘要： A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations.
摘要翻译：微电子封装在具有第一和第二半区域的衬底的表面上具有端子，每个半区域从对角线延伸，该对角线将第一表面和第一表面的相应的相对角分成两部分。用于承载前半部分中的数据和地址信息的终端提供对第一存储器存储阵列的第一存储器通道访问，并且用于承载第二半部分中的数据和地址信息的终端提供对第二存储器存储阵列的第二存储器通道访问。封装可以包括覆盖在基板的相同表面上的第一和第二微电子元件，其可以以横向取向堆叠。

8. 发明授权

US09281296B2 Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design 有权
标题翻译： BGA内存封装中的芯片堆叠技术，用于小尺寸CPU和内存主板设计
公开(公告)号：US09281296B2
公开(公告)日：2016-03-08
申请号：US14448040
申请日：2014-07-31
申请人： Invensas Corporation
发明人： Zhuowen Sun , Yong Chen , Kyong-Mo Bang
IPC分类号： H01L25/00 , H01L25/065 , H01L23/498 , H01L23/00
CPC分类号： H01L25/0657 , H01L23/49816 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05624 , H01L2224/05647 , H01L2224/16227 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/481 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/43 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00015
摘要： A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.
摘要翻译：微电子封装可以包括包括具有第一和第二相对表面的电介质元件的基板和具有平行于第一表面延伸的面的微电子元件。衬底还可以包括在第一和第二表面之间延伸的多个外围边缘，其限定基底的大致矩形或正方形的周边。所述基板还可包括多个触点和端子，所述触点位于所述第一表面处，所述端子处于所述第一或第二表面中的至少一个。微电子元件可以具有限定该面的多个边缘，并且在该表面处的多个元件触点通过基板的触点与端子电耦合。微电子元件的每个边缘可以相对于衬底的周边边缘倾斜地定向。

9. 发明授权

US10007622B2 Method for reduced load memory module 有权
公开(公告)号：US10007622B2
公开(公告)日：2018-06-26
申请号：US15481288
申请日：2017-04-06
申请人： Invensas Corporation
发明人： Zhuowen Sun , Yong Chen
IPC分类号： G06F13/16 , G11C8/12 , G06F12/06 , G11C5/06 , G11C8/06 , G11C5/04
CPC分类号： G06F13/1673 , G06F12/00 , G06F12/0623 , G06F13/1694 , G11C5/04 , G11C5/06 , G11C8/06 , G11C8/12 , H01L2224/4824 , H01L2924/15311
摘要： A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

10. 发明授权

US09691437B2 Compact microelectronic assembly having reduced spacing between controller and memory packages 有权
公开(公告)号：US09691437B2
公开(公告)日：2017-06-27
申请号：US14496159
申请日：2014-09-25
申请人： Invensas Corporation
发明人： Zhuowen Sun , Yong Chen
IPC分类号： G11C5/06 , G11C5/02 , H01L23/00
CPC分类号： G11C5/063 , G11C5/025 , H01L24/00
摘要： A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations.

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