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91. 发明申请

US20130148421A1 METHODS OF PROGRAMMING TWO TERMINAL MEMORY CELLS 有权
标题翻译：编程两个终端记忆细胞的方法
公开(公告)号：US20130148421A1
公开(公告)日：2013-06-13
申请号：US13765394
申请日：2013-02-12
申请人： SanDisk 3D LLC
发明人： Tyler J. Thorp , Roy E. Scheuerlein
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2013/0092
摘要： Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell.
摘要翻译：提供了编程两个终端存储单元的方法。一种方法包括：（a）读取包括第一，第二和第n存储器单元的存储器页的信息，该信息包括第一，第二和第N编程脉冲调谐指令; （b）根据第一编程脉冲调谐指令产生第一编程脉冲以对第一存储单元进行编程; （c）锁定所述第一存储器单元以进一步编程脉冲; （d）根据第二编程脉冲调谐指令产生第二编程脉冲以编程第二存储单元; （e）锁定所述第二存储器单元以进一步编程脉冲; 和（f）根据第n个编程脉冲调谐指令产生第n个编程脉冲以对第n个存储单元进行编程。

92. 发明申请

US20130135925A1 STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING 有权
标题翻译：用于偏移相位变化记忆阵列的可靠写入的结构和方法
公开(公告)号：US20130135925A1
公开(公告)日：2013-05-30
申请号：US13750917
申请日：2013-01-25
申请人： SANDISK 3D LLC
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/21
CPC分类号： G11C11/21 , G11C13/0004 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481
摘要： A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
摘要翻译：具有包括二极管和相变材料的存储单元的存储器阵列通过将所有未选择的存储单元维持在反向偏置状态来可靠地编程。因此，泄漏低，并且确保没有未选择的存储器单元受到干扰。为了在顺序写入期间避免干扰未选择的存储单元，在选择新的位线和字线之前，先前选择的字线和位线被带到其未选择的电压。改进的电流镜结构控制相变材料的状态切换。

93. 发明申请

US20130130467A1 RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES 有权
标题翻译：用于支柱结构的阻力特征和可拆卸间隔器双重方式
公开(公告)号：US20130130467A1
公开(公告)日：2013-05-23
申请号：US13744971
申请日：2013-01-18
申请人： SANDISK 3D LLC
发明人： Yung-Tin Chen , Steven J. Radigan
IPC分类号： H01L45/00
CPC分类号： H01L45/1691 , H01L21/0337 , H01L21/0338 , H01L27/1021
摘要： A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.
摘要翻译：提供了一种制造存储器阵列的方法，其包括在衬底上形成层，在层上形成特征，在每个特征上形成侧壁间隔物，在填充物特征之间填充相邻侧壁间隔物之间的空间，去除侧壁间隔物，特征和填料特征，并且使用特征和填料特征作为掩模来蚀刻层以形成柱状非易失性存储单元。提供了许多其他方面。

94. 发明申请

US20130121078A1 THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES AND A SINGLE-SIDED WORD LINE ARCHITECTURE 有权
标题翻译：具有垂直位线和单面字线结构的可重新编程的非易失性存储器元件的三维阵列
公开(公告)号：US20130121078A1
公开(公告)日：2013-05-16
申请号：US13735983
申请日：2013-01-07
申请人： SanDisk 3D LLC
发明人： Tianhong Yan , George Samachisa
IPC分类号： G11C16/10
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/06035 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/025 , G11C16/10 , G11C2013/0045 , G11C2013/0088 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/71 , G11C2213/75 , G11C2213/78 , H01L23/528 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.
摘要翻译：特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。单面字线架构为每行存储器元件专门提供字线，而不是在两行存储器元件之间共享一个字线，从而避免跨越字线跨越阵列链接存储元件。虽然存储器元件行也被对应的局部位线行访问，但是在局部位线的相邻行之间没有扩展耦合，因此没有扩展超出字线的漏电流。

95. 发明申请

US20130119510A1 DEVICES INCLUDING A P-I-N DIODE DISPOSED ADJACENT A SILICIDE IN SERIES WITH A DIELECTRIC MATERIAL 有权
标题翻译：包含P-I-N二极体的设备在电介质材料系列中处理邻苯二甲酸二甲酯
公开(公告)号：US20130119510A1
公开(公告)日：2013-05-16
申请号：US13705227
申请日：2012-12-05
申请人： SanDisk 3D LLC
发明人： Scott Brad Herner
IPC分类号： H01L27/06
CPC分类号： H01L27/06 , G11C13/0069 , G11C17/16 , G11C2013/009 , G11C2213/33 , H01L23/5252 , H01L27/101 , H01L27/1021 , H01L2924/0002 , H01L2924/3011 , Y10S257/91 , H01L2924/00
摘要： A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. Numerous other aspects are provided.
摘要翻译：提供了一种器件，其包括垂直取向的p-i-n二极管，其包括邻近垂直取向的p-i-n二极管设置的半导体材料，硅化物，锗化物或硅化物 - 锗化物层，以及与垂直取向的p-i-n二极管串联电介质材料。介电材料设置在第一导电层和第二导电层之间，选自HfO 2，Al 2 O 3，ZrO 2，TiO 2，La 2 O 3，Ta 2 O 5，RuO 2，ZrSiO x，AlSiO x，HfSiO x，HfAlO x，HfSiON，ZrSiAlO x， HfSiAlOx，HfSiAlON和ZrSiAlON。提供了许多其他方面。

96. 发明申请

US20130119338A1 RESISTANCE-SWITCHING MEMORY CELLS ADAPTED FOR USE AT LOW VOLTAGE 有权
标题翻译：适用于低电压使用的电阻开关存储器电池
公开(公告)号：US20130119338A1
公开(公告)日：2013-05-16
申请号：US13734517
申请日：2013-01-04
申请人： SanDisk 3D LLC
发明人： Xiaoyu Yang , Roy E. Scheuerlein , Feng Li , Albert T. Meeks
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , G11C17/00 , G11C17/16 , H01L23/5252 , H01L27/101 , H01L45/04 , H01L45/146 , H01L2924/0002 , H01L2924/00
摘要： A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided.
摘要翻译：提供存储单元，其包括与二极管串联耦合的二极管和电阻切换材料层。电阻切换材料层：（a）包括由XvOw组成的族的材料，其中X表示由Hf和Zr组成的族的元素，并且其中下标v和w具有形成稳定的非零值化合物，（b）的厚度为20至65埃。还提供其他方面。

97. 再颁专利

USRE46348E1 Program cycle skip 有权
公开(公告)号：USRE46348E1
公开(公告)日：2017-03-21
申请号：US14231591
申请日：2014-03-31
申请人： SANDISK 3D, LLC
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00 , G11C13/00 , G11C5/02 , G11C17/16 , G11C17/18
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

98. 发明授权

US09595323B1 Word line compensation for memory arrays 有权
标题翻译：存储器阵列的字线补偿
公开(公告)号：US09595323B1
公开(公告)日：2017-03-14
申请号：US15015672
申请日：2016-02-04
申请人： SanDisk 3D LLC
发明人： Yingchang Chen , Jeffrey Koonyee Lee , Chang Siau , Anurag Nigam , Thomas Yan
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C13/0023 , G11C8/08 , G11C8/14 , G11C11/16 , G11C13/0028 , G11C13/0033 , G11C2013/0054
摘要： A method is provided for operating a non-volatile storage system that includes a plurality of bit lines, a word line comb including a plurality of word lines, and a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines. The method includes receiving a current conducted by the word line comb, estimating a resistance of a conductive path between the word line comb and a selected word line voltage node, and generating a voltage at the selected word line voltage node based on the received current and the estimated resistance so that a voltage of the word line comb substantially equals a reference voltage.
摘要翻译：提供一种用于操作非易失性存储系统的方法，该非易失性存储系统包括多个位线，包括多个字线的字线梳和多个存储元件，每个存储元件耦合在一个位线和一个位线之间的字线。该方法包括接收由字线梳传导的电流，估计字线梳与选定字线电压节点之间的导电路径的电阻，以及基于所接收的电流在所选字线电压节点处产生电压，以及估计电阻使得字线梳的电压基本上等于参考电压。

99. 发明授权

US09583539B2 Word line connection for memory device and method of making thereof 有权
标题翻译：用于存储器件的字线连接及其制造方法
公开(公告)号：US09583539B2
公开(公告)日：2017-02-28
申请号：US14463113
申请日：2014-08-19
申请人： SanDisk 3D LLC
发明人： Seje Takaki
IPC分类号： H01L27/24 , H01L21/768 , H01L21/3213 , H01L27/115 , H01L27/06 , H01L45/00
CPC分类号： H01L27/2481 , H01L21/32139 , H01L21/76892 , H01L27/0688 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L45/1226 , H01L45/141 , H01L45/145 , H01L45/149 , H01L45/16
摘要： A three-dimensional monolithic memory device includes at least one device region and a plurality of contact regions each including a stack of an alternating plurality of conductive word line contact layers and insulating layers located over a substrate, where the stacks in the plurality of contact regions are separated from one another by an insulating material, and a bridge connector including a conductive material extending between a first conductive word line contact layer of a first stack in a first contact region and a second conductive word line contact layer of a second stack in a second contact region, where the first word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level.
摘要翻译：三维单片存储器件包括至少一个器件区域和多个接触区域，每个接触区域包括交替的多个导电字线接触层和位于衬底上的绝缘层的堆叠，其中多个接触区域中的堆叠通过绝缘材料彼此分离，并且桥连接器包括在第一接触区域中的第一堆叠体的第一导电字线接触层和第二层叠体的第二导电字线接触层之间延伸的导电材料第二接触区域，其中第一字线接触层在基本上平行于衬底的主表面的第一接触电平中延伸，而第二字线接触层在基本上平行于衬底的主表面的第二接触电平中延伸，不同于第一级。

100. 发明授权

US09576673B2 Sensing multiple reference levels in non-volatile storage elements 有权
标题翻译：在非易失性存储元件中检测多个参考电平
公开(公告)号：US09576673B2
公开(公告)日：2017-02-21
申请号：US14508615
申请日：2014-10-07
申请人： SanDisk 3D LLC
发明人： Xiaowei Jiang , Chang Siau , Siu Lung Chan
IPC分类号： G11C16/28 , G11C16/04 , G11C11/56 , G11C16/26 , G11C16/34
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/0466 , G11C16/0483 , G11C16/26 , G11C16/3459 , G11C2211/5621
摘要： Disclosed herein are techniques for sensing multiple reference levels in non-volatile storage elements without changing the voltage on the selected word line. One aspect includes determining a first condition of a selected non-volatile storage element with respect to a first reference level based on whether a sensing transistor conducts in response to a sense voltage on a sense node. Then, a voltage on the source terminal of the sensing transistor is modified after determining the first condition with respect to the first reference level. A second condition of the selected non-volatile storage element is then determined with respect to a second reference level based on whether the sensing transistor conducts in response to the sense voltage on the sense node. This allows two different reference levels to be efficiently sensed. Dynamic power is saved due low capacitance of the sensing transistor relative to the sense node.
摘要翻译：本文公开了用于在不改变所选字线上的电压的情况下感测非易失性存储元件中的多个参考电平的技术。一个方面包括：基于感测晶体管是否响应于感测节点上的感测电压而导致相对于第一参考电平确定所选择的非易失性存储元件的第一状态。然后，在确定相对于第一参考电平的第一条件之后修改感测晶体管的源极端子上的电压。然后，基于感测晶体管是否响应于感测节点上的感测电压导通，相对于第二参考电平来确定所选择的非易失性存储元件的第二条件。这允许有效地感测到两个不同的参考电平。由于感测晶体管相对于感测节点的低电容，动态功率得以节省。

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