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1. 发明授权

US09361976B2 Sense amplifier including a single-transistor amplifier and level shifter and methods therefor 有权
标题翻译：包括单晶体管放大器和电平转换器的感应放大器及其方法
公开(公告)号：US09361976B2
公开(公告)日：2016-06-07
申请号：US14539150
申请日：2014-11-12
申请人： SanDisk 3D LLC
发明人： Chang Siau , Yingchang Chen
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C7/067 , G11C13/0002 , G11C13/0023 , G11C13/0061 , G11C27/024 , G11C2013/0054 , G11C2213/71
摘要： Methods are provided for use with a memory array that includes a selected memory cell coupled to a selected word line and a selected bit line, with the selected word line biased at a read voltage. The method include coupling a sense amplifier to the selected bit line, the sense amplifier including a capacitor integrator, a single-transistor amplifier and a level shifter, maintaining the selected bit line at a voltage of substantially 0V using the single-transistor amplifier and the level shifter, and integrating a selected bit line current on the capacitor integrator.
摘要翻译：提供了与存储器阵列一起使用的方法，所述存储器阵列包括耦合到所选择的字线和选定位线的所选择的存储器单元，所选择的字线被偏置在读取电压。该方法包括将感测放大器耦合到所选择的位线，读出放大器包括电容器积分器，单晶体管放大器和电平转换器，使用单晶体管放大器将所选位线保持在大致0V的电压，并且电平移位器，并将所选位线电流积分到电容积分器上。

2. 发明授权

US09202566B2 Vertical cross point reram forming method 有权
标题翻译：垂直交叉点形成方法
公开(公告)号：US09202566B2
公开(公告)日：2015-12-01
申请号：US14246052
申请日：2014-04-05
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, a plurality of forming operations may be performed in which non-volatile storage elements located near the far end of a plurality of word line fingers associated with a word line comb are formed prior to forming other non-volatile storage elements. In one example, non-volatile storage elements may be formed in each of the plurality of word line fingers in parallel and in an order that forms non-volatile storage elements in each of the plurality of word line fingers that are located near the far ends of the plurality of word line fingers before forming other non-volatile storage elements. Each non-volatile storage element that is formed during a forming operation may be current limited while a forming voltage is applied across the non-volatile storage element.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，可以执行多个形成操作，其中在形成其他非易失性存储元件之前形成位于与字线梳相关联的多个字线手指的远端附近的非易失性存储元件。在一个示例中，非易失性存储元件可以并行地形成在多个字线手指中的每一个中，并且以在多个字线手指中的远端附近形成非易失性存储元件的顺序在形成其他非易失性存储元件之前的多个字线指。在成形操作期间形成的每个非易失性存储元件可以是电流限制的，同时在非易失性存储元件上施加形成电压。

3. 发明授权

US09715925B2 Methods and apparatus for vertical cross point re-RAM array bias calibration 有权
公开(公告)号：US09715925B2
公开(公告)日：2017-07-25
申请号：US14502093
申请日：2014-09-30
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0002 , G11C13/0021 , G11C13/0033 , G11C13/0038 , G11C13/0069 , G11C2013/0076 , G11C2207/2254 , G11C2213/71
摘要： Methods for operating a non-volatile storage system are described. The non-volatile storage system includes a plurality of bit lines, a plurality of word line combs each comprising a plurality of word lines, and a plurality of resistance-switching memory elements. Each resistance-switching memory element is coupled between one of the bit lines and one of the word lines. The method includes calibrating a plurality of bias voltages for the word lines and bit lines based on estimates of data values stored in the resistance-switching memory elements.

4. 发明申请

US20160042789A1 MULTIPLE LAYER FORMING SCHEME FOR VERTICAL CROSS POINT RERAM 有权
标题翻译：用于垂直交叉点RERAM的多层形成方案
公开(公告)号：US20160042789A1
公开(公告)日：2016-02-11
申请号：US14887532
申请日：2015-10-20
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，在成形操作期间，可以偏置交叉点存储器阵列，使得浪费电流被最小化或消除。在一个示例中，存储器阵列可以被偏置，使得第一字线梳被设置为第一电压，与第一字线梳交织的第二字线梳被设置为第一电压，并且选择的垂直位线被设置到第二电压，使得在要形成的非易失性存储元件上施加形成电压。在一些实施例中，存储器阵列可以包括多个字线梳状层，并且可以在所有多个字线梳状层上的非易失性存储元件上同时执行形成操作，或者多个字线梳的子集层。

5. 发明申请

US20140347912A1 SENSE AMPLIFIER LOCAL FEEDBACK TO CONTROL BIT LINE VOLTAGE 有权
标题翻译： SENSE放大器本地反馈控制位线电压
公开(公告)号：US20140347912A1
公开(公告)日：2014-11-27
申请号：US14283034
申请日：2014-05-20
申请人： SANDISK 3D LLC
发明人： Chang Siau , Xiaowei Jiang , Yingchang Chen
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/04 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C11/5642 , G11C13/0069 , G11C16/24 , G11C16/26 , G11C2013/0042 , G11C2013/0045 , G11C2207/063
摘要： Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.
摘要翻译：描述了使用闭环反馈对位线进行预充电的方法。在一个实施例中，读出放大器可以包括位线预充电电路，用于在感测连接到位线的存储器单元之前将位线设置为读取电压。位线预充电电路可以包括具有第一栅极的源极跟随器配置的第一晶体管和电耦合到位线的第一源节点。通过将来自第一源节点的本地反馈应用于第一门，可以减少位线建立时间。在一些情况下，施加到第一栅极的第一电压可以基于从第一位线汲取的第一电流来确定。因此，施加到第一栅极的第一电压可以随时间而变化，这取决于连接到位线的所选择的存储器单元的电导率。

6. 发明申请

US20140301131A1 MULTIPLE LAYER FORMING SCHEME FOR VERTICAL CROSS POINT RERAM 有权
标题翻译：用于垂直交叉点RERAM的多层形成方案
公开(公告)号：US20140301131A1
公开(公告)日：2014-10-09
申请号：US14246053
申请日：2014-04-05
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，在成形操作期间，可以偏置交叉点存储器阵列，使得浪费电流被最小化或消除。在一个示例中，存储器阵列可以被偏置，使得第一字线梳被设置为第一电压，与第一字线梳交织的第二字线梳被设置为第一电压，并且选择的垂直位线被设置到第二电压，使得在要形成的非易失性存储元件上施加形成电压。在一些实施例中，存储器阵列可以包括多个字线梳状层，并且可以在所有多个字线梳状层上的非易失性存储元件上同时执行形成操作，或者多个字线梳的子集层。

7. 发明授权

US09543009B2 Multiple layer forming scheme for vertical cross point reram 有权
标题翻译：垂直交叉点多层形成方案
公开(公告)号：US09543009B2
公开(公告)日：2017-01-10
申请号：US14887532
申请日：2015-10-20
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，在成形操作期间，可以偏置交叉点存储器阵列，使得浪费电流被最小化或消除。在一个示例中，存储器阵列可以被偏置，使得第一字线梳被设置为第一电压，与第一字线梳交织的第二字线梳被设置为第一电压，并且选择的垂直位线被设置到第二电压，使得在要形成的非易失性存储元件上施加形成电压。在一些实施例中，存储器阵列可以包括多个字线梳状层，并且可以在所有多个字线梳状层上的非易失性存储元件上同时执行形成操作，或者多个字线梳的子集层。

8. 发明申请

US20160118113A1 MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINES AND DUAL-GATE BIT LINE SELECT TRANSISTORS 有权
标题翻译：具有STAGGERED垂直位线和双栅极线选择晶体管的单个三维存储器阵列
公开(公告)号：US20160118113A1
公开(公告)日：2016-04-28
申请号：US14522777
申请日：2014-10-24
申请人： SanDisk 3D LLC
发明人： Chang Siau
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0026 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/10 , H01L45/1226 , H01L45/145 , H01L45/146
摘要： A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines.
摘要翻译：提供了一种单片三维存储器阵列，其包括设置在衬底上方的全局位线，每个全局位线具有长轴，设置在全局位线上方的垂直取向的位线，设置在全局位线上方的字线，存储器耦合在垂直取向的位线和字线之间的单元以及耦合在垂直取向的位线和全局位线之间的垂直取向的位线选择晶体管。每个垂直取向的位线选择晶体管具有宽度，第一控制端子和第二控制端子。字线和垂直取向的位线具有半间距，并且垂直取向的位线选择晶体管的宽度在半间距的约两倍和约半倍之间。设置在相邻全局位线之上的垂直位线沿着全局位线的长轴的方向彼此偏移。

9. 发明申请

US20160093374A1 METHODS AND APPARATUS FOR VERTICAL CROSS POINT RE-RAM ARRAY BIAS CALIBRATION 有权
标题翻译：用于垂直交叉点重新组合的方法和装置的阵列偏置校准
公开(公告)号：US20160093374A1
公开(公告)日：2016-03-31
申请号：US14502093
申请日：2014-09-30
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0002 , G11C13/0021 , G11C13/0033 , G11C13/0038 , G11C13/0069 , G11C2013/0076 , G11C2207/2254 , G11C2213/71
摘要： Methods for operating a non-volatile storage system are described. The non-volatile storage system includes a plurality of bit lines, a plurality of word line combs each comprising a plurality of word lines, and a plurality of resistance-switching memory elements. Each resistance-switching memory element is coupled between one of the bit lines and one of the word lines. The method includes calibrating a plurality of bias voltages for the word lines and bit lines based on estimates of data values stored in the resistance-switching memory elements.
摘要翻译：描述了用于操作非易失性存储系统的方法。非易失性存储系统包括多个位线，每个包括多个字线的多个字线梳和多个电阻切换存储元件。每个电阻切换存储元件耦合在一个位线和一条字线之间。该方法包括基于存储在电阻切换存储器元件中的数据值的估计来校准字线和位线的多个偏置电压。

10. 发明授权

US09196362B2 Multiple layer forming scheme for vertical cross point reram 有权
标题翻译：垂直交叉点多层形成方案
公开(公告)号：US09196362B2
公开(公告)日：2015-11-24
申请号：US14246053
申请日：2014-04-05
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，在成形操作期间，可以偏置交叉点存储器阵列，使得浪费电流被最小化或消除。在一个示例中，存储器阵列可以被偏置，使得第一字线梳被设置为第一电压，与第一字线梳交织的第二字线梳被设置为第一电压，并且选择的垂直位线被设置到第二电压，使得在要形成的非易失性存储元件上施加形成电压。在一些实施例中，存储器阵列可以包括多个字线梳状层，并且可以在所有多个字线梳状层上的非易失性存储元件上同时执行形成操作，或者多个字线梳的子集层。

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