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1. 发明申请

US20180046598A1 MEMORY DEVICE FOR MATRIX-VECTOR MULTIPLICATIONS 审中-公开
公开(公告)号：US20180046598A1
公开(公告)日：2018-02-15
申请号：US15235157
申请日：2016-08-12
申请人： International Business Machines Corporation
发明人： Manuel Le Gallo , Abu Sebastian
IPC分类号： G06F17/16 , G11C13/00 , G11C13/04
CPC分类号： G06F17/16 , G11C11/16 , G11C11/56 , G11C11/5607 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C13/04 , G11C13/047
摘要： A device for performing a multiplication of a matrix with a vector. The device comprises a plurality of memory elements, a signal generator and a readout circuit. The signal generator is configured to apply programming signals to the memory elements. The signal generator is further configured to control a first signal parameter of the programming signals in dependence on matrix elements of the matrix and to control a second signal parameter of the programming signals in dependence on vector elements of the vector. The readout circuit is configured to read out memory values of the memory elements. The memory values represent result values of vector elements of a product vector of the multiplication. The memory elements may be in particular resistive memory elements or photonic memory elements. Additionally there is provided a related method and design structure for performing the multiplication of a matrix with a vector.

2. 发明授权

US09530493B2 Resistive random-access memory cells 有权
标题翻译：电阻随机存取存储器单元
公开(公告)号：US09530493B2
公开(公告)日：2016-12-27
申请号：US15070716
申请日：2016-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Evangelos S Eleftheriou , Daniel Krebs , Abu Sebastian
IPC分类号： G11C13/00 , G11C11/56 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0011 , G11C11/5614 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0069 , G11C2213/18 , G11C2213/35 , G11C2213/52 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/1253 , H01L45/16
摘要： Improved random-access memory cells, complementary cells, and memory devices. The present invention provides a RRAM cell for storing information in a plurality of programmable cell states. The RRAM cell includes: an electrically-insulating matrix located between a first electrode and a second electrode such that an electrically-conductive path, extending in a direction between said electrodes, is formed within said matrix on application of a write voltage to said electrodes; an electrically-conductive component; wherein a resistance is presented by the electrically-conductive component; and wherein said RRAM is arranged such that said resistance is at least about that of said electrically-conductive path and at most about that of said electrically-insulating matrix in any of said plurality of programmable cell states.
摘要翻译：改进的随机存取存储器单元，互补单元和存储器件。本发明提供一种用于存储多个可编程单元状态的信息的RRAM单元。 RRAM单元包括：位于第一电极和第二电极之间的电绝缘基体，使得在对所述电极施加写入电压时，在所述矩阵内形成沿所述电极之间的方向延伸的导电路径; 导电部件; 其中由所述导电部件呈现电阻; 并且其中所述RRAM布置成使得所述电阻至少约为所述导电路径的电阻，并且至多约等于所述多个可编程单元状态中的任一个中的所述电绝缘矩阵的电阻。

3. 发明授权

US09484088B2 Permutational memory cells 有权
标题翻译：占位记忆细胞
公开(公告)号：US09484088B2
公开(公告)日：2016-11-01
申请号：US14665794
申请日：2015-03-23
申请人： Micron Technology, Inc.
发明人： Scott E. Sills
IPC分类号： G11C5/02 , G11C5/06 , G11C13/00 , G11C11/00 , G11C11/50 , G11C7/18 , G11C8/00 , G11C11/56 , G11C8/14 , G11C19/00
CPC分类号： G11C13/0011 , G11C5/02 , G11C5/06 , G11C7/18 , G11C8/00 , G11C8/14 , G11C11/00 , G11C11/50 , G11C11/56 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C19/00 , G11C2213/52
摘要： Various embodiments include at least one resistance change memory (RCM) cell, In one embodiment, three or more pairs of electrical contacts are coupled to the at least one RCM cell. A first portion of the pairs are arranged laterally to one another in a first grouping and a second opposing portion of the pairs are arranged laterally to one another in a second grouping. A memory cell material is disposed between opposing sides of the pairs of the three or more electrical contacts. The memory cell material is configured to form a conductive pathway between one or more of the pairs, with each of the three or more pairs being configured to be accessed individually for at least one operation including program, erase, and read operations. Additional apparatuses and methods are described.
摘要翻译：各种实施例包括至少一个电阻变化存储器（RCM）单元。在一个实施例中，三个或更多对电触点耦合到至少一个RCM单元。成对的第一部分在第一组中彼此横向地布置，并且对的第二相对部分在第二组中彼此横向地布置。存储单元材料设置在三个或更多个电触点对的相对侧之间。存储单元材料被配置为在一对或多对之间形成导电路径，其中三对或更多对中的每一对被配置为分别访问包括程序，擦除和读取操作的至少一个操作。描述附加的装置和方法。

4. 发明授权

US09443586B2 Nonvolatile memory device, memory system including the same and method for driving nonvolatile memory device 有权
标题翻译：非易失性存储器件，包括相同的存储器系统和用于驱动非易失性存储器件的方法
公开(公告)号：US09443586B2
公开(公告)日：2016-09-13
申请号：US14680496
申请日：2015-04-07
申请人： Hyun-Kook Park
发明人： Hyun-Kook Park
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile memory device can improve a read retry operation speed while minimizing a reduction in the capability of a memory read operation by performing a read retry operation. The nonvolatile memory device includes a resistive memory cell, a sensing node, and a sense amplifier connected to the sensing node and sensing a difference between a voltage level of the sensing node and a reference voltage level or a difference between a current level of the sensing node and a reference current level. When a read fail bit value is generated during a read operation of data stored in the resistive memory cell, a current flowing in the resistive memory cell is changed by changing a difference between voltages of opposite ends of the resistive memory cell and a read retry operation is then performed.
摘要翻译：非易失性存储器件可以通过执行读取重试操作来最小化存储器读取操作的能力，从而提高读取重试操作速度。非易失性存储器件包括电阻存储器单元，感测节点和连接到感测节点的感测放大器，并感测感测节点的电压电平与参考电压电平之间的差值，或感测节点的当前电平之间的差值节点和参考电流水平。当在存储在电阻性存储单元中的数据的读取操作期间产生读取失败位值时，通过改变电阻性存储单元的相对端的电压和读取重试操作之间的差异来改变在电阻性存储单元中流动的电流然后执行。

5. 发明申请

US20160225444A1 Memory Sense Amplifiers and Memory Verification Methods 有权
公开(公告)号：US20160225444A1
公开(公告)日：2016-08-04
申请号：US15096135
申请日：2016-04-11
申请人： Micron Technology, Inc.
发明人： Makoto Kitagawa , Kerry Tedrow
IPC分类号： G11C13/00
CPC分类号： G11C13/0064 , G11C7/062 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0054 , G11C2213/79
摘要： Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

6. 发明申请

US20160155502A1 Method for Operating a Conductive Bridging Memory Device 有权
标题翻译：用于操作导电桥接存储器件的方法
公开(公告)号：US20160155502A1
公开(公告)日：2016-06-02
申请号：US14957249
申请日：2015-12-02
申请人： Katholieke Universiteit Leuven, KU LEUVEN R&D , IMEC VZW
发明人： Ludovic Goux , Attilio Belmonte
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0011 , G11C2013/0078 , G11C2013/0083 , G11C2013/0088 , G11C2013/0092 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (tf) of 100 ns or less and a pulse amplitude (If) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (ts) of 100 ns or less and a pulse amplitude (Is) equal to or larger than the forming current pulse amplitude (If).
摘要翻译：公开了一种用于操作导电桥随机存取存储器（CBRAM）器件的方法，该器件包括夹在阳离子供应顶电极和底电极之间的电解质元件。该方法包括通过施加具有100ns或更小的脉冲宽度（tf）和10uA或更小的脉冲幅度（If）的形成电流脉冲来调节CBRAM器件，并且当编程时，将经调节的CBRAM器件设置为低通过施加具有100ns以下的脉冲宽度（ts）的设定电流脉冲和等于或大于成形电流脉冲振幅（If）的脉冲幅度（Is）的电阻状态（LRS）。

7. 发明授权

US09355732B2 Latch initialization for a data storage device 有权
标题翻译：数据存储设备的锁存初始化
公开(公告)号：US09355732B2
公开(公告)日：2016-05-31
申请号：US14504268
申请日：2014-10-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： Menahem Lasser
IPC分类号： G11C16/10 , G11C16/20 , G11C11/56
CPC分类号： G11C16/20 , G11C7/1006 , G11C7/1009 , G11C7/1087 , G11C7/20 , G11C11/5614 , G11C11/5628 , G11C11/5671 , G11C13/0033 , G11C13/0069 , G11C16/10 , G11C16/3427
摘要： A data storage device may include a memory die. The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write operation to write information to the memory. The method may further include loading a set of bits into the latch prior to receiving the information at the memory die. The set of bits includes at least a first bit having a first value and a second bit having a second value that is different than the first value. The method further includes receiving the information at the memory die and overwriting at least a portion of the set of bits at the latch with the information.
摘要翻译：数据存储设备可以包括存储器管芯。存储器管芯包括存储器和锁存器。方法可以包括接收与写入操作相对应的命令以将信息写入存储器。该方法还可以包括在接收存储器管芯之前的信息时将一组位加载到锁存器中。所述位组包括具有第一值的至少第一位和具有不同于第一值的第二值的第二位。所述方法还包括在所述存储器管芯处接收所述信息，并用所述信息重写所述锁存器中的所述一组位的至少一部分。

8. 发明授权

US09349440B1 Non-volatile SRAM with multiple storage states 有权
标题翻译：具有多种存储状态的非易失性SRAM
公开(公告)号：US09349440B1
公开(公告)日：2016-05-24
申请号：US14567414
申请日：2014-12-11
申请人： Empire Technology Development LLC
发明人： Yanjun Ma
IPC分类号： G11C11/00 , G11C11/56 , G11C11/413 , G11C13/00
CPC分类号： G11C11/56 , G11C11/413 , G11C11/419 , G11C11/5607 , G11C11/5614 , G11C11/565 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C14/0081 , G11C14/009 , G11C17/16 , G11C17/18 , G11C2213/33
摘要： Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. The multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include one or more programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.
摘要翻译：这里通常描述了具有多个存储状态的非易失性静态随机存取存储器件的技术。多存储状态非易失性随机存取存储器件具有两个或多个存储器单元。每个存储器单元可以包括一个或多个可编程电阻器件，其可被动态地编程以将存储器单元配置在特定的逻辑状态。

9. 发明授权

US09336876B1 Soak time programming for two-terminal memory 有权
标题翻译：浸泡时间编程为两端存储器
公开(公告)号：US09336876B1
公开(公告)日：2016-05-10
申请号：US14214108
申请日：2014-03-14
申请人： Crossbar, Inc.
发明人： Tanmay Kumar , Layne Armijo , Sung Hyun Jo
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/1675 , G11C11/5614 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2013/0078 , G11C2013/0092 , G11C2213/33 , G11C2213/51
摘要： Providing for improved programming techniques for endurance and memory retention in two-terminal memory is described herein. In some embodiments, a programming pulse can be configured to provide a minimum pulse time over which a program signal is applied to a two-terminal memory cell, following programming of the two-terminal memory cell. This minimum pulse time can help to stabilize the program state of the two-terminal memory cell, improving stability of the program state (e.g., related to memory retention) and overall increased endurance (e.g., in program cycles) of the two-terminal memory cell. The minimum pulse time can be initiated separately to a programming pulse, or can be integrated as part of the program pulse, in various embodiments. In some embodiments, current compliance or voltage control can be implemented in conjunction with providing programming and minimum pulse time functionality.
摘要翻译：这里描述了提供用于双端存储器中的耐久性和存储器保持的改进的编程技术。在一些实施例中，编程脉冲可以被配置为在二端存储器单元的编程之后提供将编程信号施加到两端存储单元的最小脉冲时间。这个最小脉冲时间可以帮助稳定两端存储单元的编程状态，改善程序状态的稳定性（例如，与存储器保持有关）和整体增加的两端存储器的耐久性（例如，在程序周期中）细胞。在各种实施例中，最小脉冲时间可以单独地开始到编程脉冲，或者可以被集成为编程脉冲的一部分。在一些实施例中，可以结合提供编程和最小脉冲时间功能来实现电流顺应性或电压控制。

10. 发明授权

US09311997B2 Resistive memory device with word lines coupled to multiple sink transistors 有权
标题翻译：具有耦合到多个晶体管的字线的电阻式存储器件
公开(公告)号：US09311997B2
公开(公告)日：2016-04-12
申请号：US14069499
申请日：2013-11-01
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yongkyu Lee , Sungyeon Lee , Yeongtaek Lee
IPC分类号： G11C13/00 , G11C11/56 , G11C29/50 , G11C29/52 , G11C7/10 , G11C8/16 , G11C11/00 , G11C29/04
CPC分类号： G11C13/004 , G11C7/1075 , G11C8/16 , G11C11/005 , G11C11/5607 , G11C11/5614 , G11C11/5642 , G11C11/5657 , G11C11/5678 , G11C29/50008 , G11C29/52 , G11C2013/0054 , G11C2029/0409 , G11C2029/0411 , G11C2213/72
摘要： A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line. One of the first sink transistors is disposed between one end of the row line and a ground and the other of the first sink transistors is disposed between an opposite end of the row line and the ground. One of the second sink transistors is disposed between one end of the reference row line and the ground and the other of the second sink transistors is disposed between an opposite end of the reference row line and the ground. The word line is coupled to gates of the first and second sink transistors.
摘要翻译：电阻式存储器件包括存储单元阵列块，参考单元阵列块，两个第一和第二宿晶体管以及字线。每个存储单元阵列块包括行线，并且参考单元阵列块包括参考行线。第一个晶体管中的一个设置在行线的一端和地之间，而另一个第一宿晶体管设置在行线的相对端和地之间。第二宿晶体管中的一个设置在参考行线的一端和地之间，另一个第二宿晶体管设置在参考行线的相对端和地之间。字线耦合到第一和第二宿晶体管的栅极。

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