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91. 发明授权

US08223549B2 NAND flash memory programming 有权
标题翻译： NAND闪存编程
公开(公告)号：US08223549B2
公开(公告)日：2012-07-17
申请号：US12627448
申请日：2009-11-30
申请人： Seiichi Aritome , Haitao Liu , Di Li
发明人： Seiichi Aritome , Haitao Liu , Di Li
IPC分类号： G11C11/34
CPC分类号： G11C16/12
摘要： A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.
摘要翻译：用于防止短沟道源侧选择栅极结构中的穿通的编程方法和存储器结构包括调整所选择和未选择的位线上的电压以及编程，通过和选择栅极电压。

92. 发明申请

US20120176838A1 REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE 有权
标题翻译：减少程序干扰对存储器件的影响
公开(公告)号：US20120176838A1
公开(公告)日：2012-07-12
申请号：US13428241
申请日：2012-03-23
申请人： Seiichi ARITOME
发明人： Seiichi ARITOME
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage.
摘要翻译：一种用编程电压偏置选定字线的编程方法。源极侧的未选字线和所选择的字线的漏极侧的未选字线被偏置在小于正常通过电压的通过电压。这些未选择的字线都位于与所选字线预定的距离处。剩下的字线以正常通过电压偏置。

93. 发明授权

US08208278B2 Couplings within memory devices 有权
标题翻译：存储器件内的联轴器
公开(公告)号：US08208278B2
公开(公告)日：2012-06-26
申请号：US12637163
申请日：2009-12-14
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C5/06
CPC分类号： G11C7/02 , G11C7/1036 , H01L27/105 , H01L27/11517 , H01L27/11526
摘要： A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.
摘要翻译：存储器件包括耦合到第一多路复用器门的第一源极/漏极区域的第一位线，耦合到第二多路复用器栅极的第一源极/漏极区域的第二位线以及耦合到第二多路复用器栅极的输入的感测器件第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第二源极/漏极区域。感测装置的输入形成在与形成第一和第二位线中的至少一个的垂直电平不同的垂直电平处。

94. 发明申请

US20120106248A1 NON-VOLATILE MULTILEVEL MEMORY CELLS 有权
标题翻译：非挥发性多层记忆细胞
公开(公告)号：US20120106248A1
公开(公告)日：2012-05-03
申请号：US13343023
申请日：2012-01-04
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/10
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5641 , G11C2211/5648
摘要： The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.
摘要翻译：本公开包括用于操作非易失性多电平存储器单元的方法，设备，模块和系统。一种方法实施例包括向耦合到行选择线的第一单元分配可以对第一单元编程的第一数量的编程状态。该方法包括将耦合到行选择线的第二单元分配给可编程第二单元的第二数量的编程状态，其中第二数量的编程状态大于第一数量的编程状态。该方法包括在将第二单元编程到第二数量的编程状态之前将第一单元编程为第一数量的编程状态之一。

95. 发明授权

US08164950B2 Reduction of punch-through disturb during programming of a memory device 有权
标题翻译：减少存储设备编程期间的穿通干扰
公开(公告)号：US08164950B2
公开(公告)日：2012-04-24
申请号：US12778524
申请日：2010-05-12
申请人： Alessandro Torsi , Carlo Musilli , Seiichi Aritome
发明人： Alessandro Torsi , Carlo Musilli , Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.
摘要翻译：可以通过在编程电压下偏置所选择的字线来对所选存储单元进行编程来减少存储器件中的穿通干扰效应，以Vpass电压偏置串联串的漏极侧的字线，关闭相邻的存储单元，并且以小于Vpass的Vlow电压偏置关断存储单元的源极侧的剩余字线。

96. 发明授权

US08129781B2 Method of forming memory devices by performing halogen ion implantation and diffusion processes 有权
标题翻译：通过卤素离子注入和扩散工艺形成存储器件的方法
公开(公告)号：US08129781B2
公开(公告)日：2012-03-06
申请号：US12892691
申请日：2010-09-28
申请人： Kirk D Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
发明人： Kirk D Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/22 , H01L21/265 , H01L21/26506 , H01L21/324 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/6659 , H01L29/66659 , H01L29/788
摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
摘要翻译：公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中线结构。

97. 发明授权

US08072814B2 NAND with back biased operation 有权
标题翻译： NAND具有反向偏置运算
公开(公告)号：US08072814B2
公开(公告)日：2011-12-06
申请号：US12771211
申请日：2010-04-30
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts.
摘要翻译：公开了编程，读取和擦除存储器单元的方法。在至少一个实施例中，存储器中的程序，感测和擦除操作是通过反向偏置操作进行的，例如改进串驱动器和位线驱动器中的高电压器件隔离和截止，并且电路的任何节点都不偏零伏。

98. 发明授权

US08059474B2 Reducing read failure in a memory device 有权
标题翻译：减少存储设备中的读取失败
公开(公告)号：US08059474B2
公开(公告)日：2011-11-15
申请号：US12706357
申请日：2010-02-16
申请人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
发明人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C16/3427
摘要： Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
摘要翻译：在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。如果所选字线更靠近源极侧，则使用较低的读通过电压。在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。

99. 发明申请

US20110266610A1 MEMORY DEVICES HAVING REDUCED INTERFERENCE BETWEEN FLOATING GATES AND METHODS OF FABRICATING SUCH DEVICES 有权
标题翻译：具有浮动门之间的减少的干扰的记忆装置和制造这种装置的方法
公开(公告)号：US20110266610A1
公开(公告)日：2011-11-03
申请号：US13180361
申请日：2011-07-11
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L29/788
CPC分类号： H01L21/762 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.
摘要翻译：一种存储器阵列，包括相对于彼此具有隔离的栅极间电介质区域的晶体管。晶体管被形成为使得阵列中的每个晶体管具有电荷存储区域，例如浮置栅极，控制栅极和栅极之间的介电层。每个晶体管的栅极间电介质层与阵列中的每个其它晶体管的栅极间电介质隔离。

100. 发明申请

US20110249494A1 MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS 有权
标题翻译：多个选择门与非易失性记忆细胞
公开(公告)号：US20110249494A1
公开(公告)日：2011-10-13
申请号：US13164813
申请日：2011-06-21
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04 , G11C16/26 , G11C16/14 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.
摘要翻译：描述与非易失性存储器单元相关联的多个选择门。各种实施例包括多个选择栅极结构，工艺和操作及其对存储器件，模块和系统的适用性。在一个实施例中描述了存储器阵列。存储器阵列包括多个与多个非易失性存储器单元串联耦合的选择栅极。第一选择栅极包括电连接在一起的控制栅极和浮置栅极，第二选择栅极包括由电介质层电隔离的控制栅极和浮置栅极。

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