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91. 发明授权

US08878280B2 Flash memory device and method for manufacturing the same 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US08878280B2
公开(公告)日：2014-11-04
申请号：US13148265
申请日：2011-02-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/788 , H01L27/115 , H01L29/66 , H01L21/84 , H01L27/12
CPC分类号： H01L27/1211 , H01L21/845 , H01L27/11521 , H01L29/66803 , H01L29/66825 , H01L29/7881
摘要： The present invention provides a FinFET flash memory device and the method for manufacturing the same. The flash memory device is on an insulating layer, comprising: a first fin and a second fin, wherein the second fin is a control gate of the device; a gate dielectric layer, at side walls and top of the first fin and the second fin; source/drain regions, inside the first fin at both sides of a floating gate.
摘要翻译：本发明提供一种FinFET闪速存储器件及其制造方法。闪存器件在绝缘层上，包括：第一鳍片和第二鳍片，其中第二鳍片是器件的控制栅极; 栅极电介质层，位于第一鳍片和第二鳍片的侧壁和顶部; 源极/漏极区域，位于浮动栅极两侧的第一鳍片内。

92. 发明申请

US20140225200A1 Enhancing MOSFET Performance With Corner Stresses of STI 有权
标题翻译：通过STI的角应力提高MOSFET性能
公开(公告)号：US20140225200A1
公开(公告)日：2014-08-14
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

93. 发明授权

US08803208B2 Method for fabricating contact electrode and semiconductor device 有权
标题翻译：接触电极和半导体器件的制造方法
公开(公告)号：US08803208B2
公开(公告)日：2014-08-12
申请号：US13129075
申请日：2011-02-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/8234 , H01L23/485 , H01L29/66 , H01L29/417
CPC分类号： H01L23/485 , H01L29/41775 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described.
摘要翻译：本发明提供了一种半导体器件，包括：衬底; 形成在基板上的栅极; 源极和漏极分别位于栅极的相对侧上; 接触件，其与源极和/或漏极接触，其中接触件在与源极和/或漏极接触的端部处具有扩大的端部。在本发明中，由于在与源极/漏极接触的界面上接触面的接触面积增加，所以可以降低接触电阻，能够保证/提高半导体器件的性能。本发明还提供如前所述制造半导体器件（特别是其中的接触）的方法。

94. 发明授权

US08742545B2 Substrate strip plate structure for semiconductor device and method of manufacturing the same 有权
标题翻译：用于半导体器件的基板带状板结构及其制造方法
公开(公告)号：US08742545B2
公开(公告)日：2014-06-03
申请号：US13264063
申请日：2010-04-14
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/06 , H01L21/308
CPC分类号： H01L31/0392 , H01L31/035281 , Y02E10/50
摘要： A strip plate structure and a method of manufacturing the same are disclosed. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing. Each of the strip plates includes a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets. Each strip sheet alternately abuts either the first surfaces or the second surfaces of two adjacent strip plates.
摘要翻译：公开了一种带状板结构及其制造方法。在一个实施例中，带状板结构包括带板阵列，其包括以预定方向间隔布置的多个带状板。每个带状板包括面向带状板结构的一个侧面方向的第一表面和面向带状板结构的基本相反的侧面方向的第二表面; 和多个条状片。每个条带交替地邻接两个相邻带状板的第一表面或第二表面。

95. 发明授权

US08722524B2 Method for forming a semiconductor device including replacing material of dummy gate stacks with other conductive material 有权
标题翻译：用于形成半导体器件的方法，包括用其它导电材料代替伪栅极堆叠的材料
公开(公告)号：US08722524B2
公开(公告)日：2014-05-13
申请号：US13380362
申请日：2011-02-27
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , H01L21/823418 , H01L29/49 , H01L29/66545 , H01L29/7833
摘要： It is provided a method for forming a semiconductor device comprising: forming a material layer which exposes dummy gates and sidewall spacers and fills spaces between two adjacent gate stacks, and the material of the material layer is the same as the material of the dummy gate; removing the dummy gates and the material layer to form recesses; filling the recesses with a conductive material, and planarizing the conductive material to expose the sidewall spacers; breaking the conductive material outside the sidewall spacers to form at least two conductors, each of the conductors being only in contact with the active region at one side outside one of the sidewall spacers, so as to form gate stack structures and first contacts. Besides, a semiconductor device is provided. The method and the semiconductor device are favorable for extending process windows in forming contacts.
摘要翻译：提供一种用于形成半导体器件的方法，包括：形成暴露伪栅极和侧壁间隔物并填充两个相邻栅极堆叠之间的空间的材料层，并且材料层的材料与虚拟栅极的材料相同; 去除虚拟门和材料层以形成凹槽; 用导电材料填充凹部，并平坦化导电材料以暴露侧壁间隔物; 将导电材料破坏在侧壁间隔物外部以形成至少两个导体，每个导体仅在侧壁间隔件之外的一侧处与有源区域接触，以便形成栅叠层结构和第一触点。此外，提供了半导体器件。该方法和半导体器件有利于在形成触点时延长工艺窗口。

96. 发明申请

US20140124859A1 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140124859A1
公开(公告)日：2014-05-08
申请号：US13380857
申请日：2011-08-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/28 , H01L29/78 , H01L29/423
CPC分类号： H01L21/28008 , H01L29/41733 , H01L29/4232 , H01L29/66545 , H01L29/66643 , H01L29/66772 , H01L29/78 , H01L29/7839
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method. The manufacturing method and the semiconductor structure according to the present invention make it possible to reduce capacitance between a metal layer and a body silicon layer of an SOI substrate when a semiconductor device is in operation, which is therefore favorable for enhancing performance of the semiconductor device.
摘要翻译：本发明提供一种制造半导体结构的方法，其包括：提供SOI衬底，在SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和SOI衬底的BOX层以形成沟槽，沟槽暴露BOX层并部分延伸到BOX层中; 在沟槽的侧壁上形成侧壁间隔物; 在所述沟槽内部形成覆盖所述侧壁间隔物的金属层，其中所述金属层与所述栅极结构下方的所述SOI层接触。因此，本发明还提供根据上述方法形成的半导体结构。根据本发明的制造方法和半导体结构使半导体器件工作时能够减小SOI衬底的金属层与体硅层之间的电容，因此有利于提高半导体器件的性能。

97. 发明授权

US08673704B2 FinFET and method for manufacturing the same 有权
标题翻译： FinFET及其制造方法
公开(公告)号：US08673704B2
公开(公告)日：2014-03-18
申请号：US13579192
申请日：2012-05-14
申请人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L29/785
摘要： A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.
摘要翻译：公开了一种FinFET及其制造方法。 FinFET包括在半导体衬底上的蚀刻停止层; 在蚀刻停止层上的半导体鳍片; 栅极导体，其在与半导体鳍片的长度方向垂直的方向上延伸并覆盖半导体鳍片的至少两个侧面; 在栅极导体和半导体鳍片之间的栅介质层; 源极区和漏极区，分别设置在半导体鳍的两端; 以及与栅极电介质层下方的蚀刻停止层相邻的层间绝缘层，并且将栅极导体与蚀刻停止层和半导体鳍分离。 FinFET的鳍的高度近似等于用于形成半导体鳍的半导体层的厚度。

98. 发明授权

US08673701B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08673701B2
公开(公告)日：2014-03-18
申请号：US13376247
申请日：2011-08-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823828 , H01L21/823878 , H01L27/1203 , H01L29/4908 , H01L29/78603 , H01L29/78612
摘要： The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括：SOI衬底和形成在SOI衬底上的MOSFET，其中SOI衬底以自顶向下的方式包括SOI层，第一掩埋绝缘体层，埋入半导体层，第二掩埋绝缘体层和半导体衬底，所述掩埋半导体层包括背栅区，所述背栅区包括掺杂有第一极性的掺杂剂的所述掩埋半导体层的一部分; MOSFET包括栅极堆叠和源极/漏极区，栅极堆叠形成在SOI层上，并且源极/漏极区域形成在栅极堆叠的相对侧的SOI层中; 并且所述背栅区域包括反掺杂区域，所述反掺杂区域与所述栅叠层自对准并且包括第二极性的掺杂剂，并且所述第二极性与所述第一极性相反。本公开的实施例可以用于调整MOSFET的阈值电压。

99. 发明授权

US08664054B2 Method for forming semiconductor structure 有权
标题翻译：半导体结构形成方法
公开(公告)号：US08664054B2
公开(公告)日：2014-03-04
申请号：US13381014
申请日：2011-04-18
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823828 , H01L29/7833 , H01L29/7847 , H01L29/7848
摘要： The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.
摘要翻译：本发明涉及一种形成半导体结构的方法，包括：提供包括形成在其上的虚拟栅极的半导体衬底，围绕伪栅极的间隔物，分别形成在虚拟栅极两侧的源区和漏区，以及形成在半导体衬底中并在虚拟栅极之下的沟道区; 去除虚拟门以形成门开口; 在闸门开口处形成应力材料层; 对所述半导体基板进行退火，所述应力材料层在退火时具有拉伸应力特性; 去除闸门开口中的应力材料层; 并在门开口形成门。通过上述步骤，可以将应力记忆技术应用于pMOSFET。

100. 发明授权

US08610275B2 Semiconductor contact structure including a spacer formed within a via and method of manufacturing the same 有权
标题翻译：包括在通孔内形成的间隔物的半导体接触结构及其制造方法
公开(公告)号：US08610275B2
公开(公告)日：2013-12-17
申请号：US12996721
申请日：2010-09-27
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L23/522 , H01L21/441
CPC分类号： H01L23/5226 , H01L21/76808 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor.
摘要翻译：本发明公开了一种半导体结构及其制造方法。半导体结构包括半导体衬底，连接到半导体衬底的局部互连结构以及电连接到局部互连结构的至少一个通孔堆叠结构，其中至少一个通孔堆叠结构包括具有上通孔和下通孔，上通孔的宽度大于下通孔的宽度; 形成在靠近下通道的内壁的通孔间隔件; 覆盖通孔和通孔间隔物的表面的绝缘层; 形成在由所述绝缘层包围的空间内并且电连接到所述局部互连结构的导电插塞。本发明可应用于半导体制造领域中的通孔叠层的制造。

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