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91. 发明申请

US20050178657A1 Systems and methods of plating via interconnects 审中-公开
标题翻译：通过互连电镀的系统和方法
公开(公告)号：US20050178657A1
公开(公告)日：2005-08-18
申请号：US11099066
申请日：2005-04-05
申请人： Kyle Kirby , Warren Farnworth
发明人： Kyle Kirby , Warren Farnworth
IPC分类号： H01L21/288 , H01L21/768 , H01L23/48 , C25D1/00 , C25D5/38 , H01L21/44
CPC分类号： H01L21/2885 , H01L21/76898 , H01L23/481 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , Y10S438/928 , H01L2924/014
摘要： Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution containing a conductive material in solution with the active surface semiconductor substrate isolated therefrom. An electric potential is applied across the conductive element through the electroplating solution and a conductive contact pad in direct or indirect electrical communication with the conductive element at the closed end of the at least one via (or forming such conductive element) to cause conductive material to electrochemically deposit from the electroplating solution and fill the at least one via. Semiconductor devices and in-process semiconductor devices are also disclosed.
摘要翻译：用导电材料填充高纵横比孔的方法。在半导体衬底的背面形成至少一个高宽比通孔。至少一个通孔在一端由形成半导体衬底的导电结构的导电元件封闭。将半导体衬底的背面暴露于含有与其分离的活性表面半导体衬底的溶液中的导电材料的电镀溶液。电导通过电镀溶液施加在导电元件上，导电接触焊盘在至少一个通孔的封闭端（或形成这种导电元件）与导电元件直接或间接电连通，以使导电材料从电镀溶液电化学沉积并填充至少一个通孔。还公开了半导体器件和工艺中半导体器件。

92. 发明申请

US20050116351A1 Semiconductor interconnect having conductive spring contacts 失效
标题翻译：具有导电弹簧触点的半导体互连
公开(公告)号：US20050116351A1
公开(公告)日：2005-06-02
申请号：US11031160
申请日：2005-01-06
申请人： Kyle Kirby , Warren Farnworth
发明人： Kyle Kirby , Warren Farnworth
IPC分类号： G01R1/067 , H01L23/48 , H01L23/498 , H05K3/32 , H05K3/40
CPC分类号： G01R1/06733 , B33Y70/00 , B33Y80/00 , G01R1/06711 , G01R1/07314 , G01R3/00 , H01L23/49811 , H01L24/72 , H01L2224/05571 , H01L2224/05573 , H01L2224/13011 , H01L2224/13019 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H05K3/326 , H05K3/4092 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.
摘要翻译：用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。每个互连触点包括形成为导电弹簧元件的柔性导电层。此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

93. 发明申请

US20050104228A1 Microelectronic devices, methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices 有权
标题翻译：微电子器件，用于在微电子器件中形成通孔的方法，以及用于封装微电子器件的方法
公开(公告)号：US20050104228A1
公开(公告)日：2005-05-19
申请号：US10713878
申请日：2003-11-13
申请人： Sidney Rigg , Charles Watkins , Kyle Kirby , Peter Benson , Salman Akram
发明人： Sidney Rigg , Charles Watkins , Kyle Kirby , Peter Benson , Salman Akram
IPC分类号： H01L21/768 , H01L23/48 , H01L25/065 , H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/48091 , H01L2224/48227 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.
摘要翻译：本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微特征工件和管芯中形成通路和导电互连的方法。在一个实施例中，一种方法包括在具有集成电路的管芯上形成接合焊盘，所述接合焊盘电耦合到集成电路。然后在管芯上形成导线，导电线具有附接到接合焊盘的第一端部和与接合焊盘间隔开的第二端部。该方法还可以包括形成通过管芯，接合焊盘和导电线的第一端部的通孔或通道，以及在通道的至少一部分中沉积导电材料以形成延伸在最不通常地通过微电子器件。

94. 发明申请

US20050077913A1 Compliant contact structures, contactor cards and test system including same, and methods of fabrication and use 有权
标题翻译：接触结构合适，接触器卡和包括其的测试系统以及制造和使用方法
公开(公告)号：US20050077913A1
公开(公告)日：2005-04-14
申请号：US10684621
申请日：2003-10-14
申请人： Charles Watkins , Kyle Kirby
发明人： Charles Watkins , Kyle Kirby
IPC分类号： G01R1/067 , G01R1/073 , G01R31/28 , G01R31/02
CPC分类号： G01R1/07357 , G01R1/06711 , G01R1/0735 , G01R31/2831 , G01R31/2887 , H01L2924/0002 , Y10T29/49002 , Y10T29/49004 , Y10T29/49117 , Y10T29/4913 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155 , Y10T29/4916 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T29/49204 , H01L2924/00
摘要： A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least another portion integral with the fixed portion, laterally unsupported within a thickness of the substrate and extending beyond a side thereof. Dual-sided compliant contact structures, methods of forming compliant contact structures, a method of testing a semiconductor device and a testing system are also disclosed.
摘要翻译：用于与要测试的半导体器件可操作地耦合的柔性接触结构和接触器卡包括在其中形成有柔性接触件的基本上平面的基板。柔性接触结构包括固定在基底内的部分和与固定部分成一体的至少另一部分，横向地不支撑在基底的厚度内并延伸超过其一侧。还公开了双面柔性接触结构，形成柔性接触结构的方法，测试半导体器件和测试系统的方法。

95. 发明申请

US20050046431A1 PROBE CARD FOR USE WITH MICROELECTRONIC COMPONENTS,AND METHODS FOR MAKING SAME 失效
标题翻译：用微电子元件使用的探针卡及其制造方法
公开(公告)号：US20050046431A1
公开(公告)日：2005-03-03
申请号：US10653766
申请日：2003-09-03
申请人： Kyle Kirby
发明人： Kyle Kirby
IPC分类号： G01R3/00 , G01R31/28 , H05K3/32 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： G01R31/2886 , G01R3/00 , H01L2924/15184 , H05K3/326 , H05K3/4007 , H05K3/4092 , H05K3/423 , H05K2201/0367 , H05K2201/09563 , H05K2201/0969 , Y10T29/49002 , Y10T29/49004 , Y10T29/49126
摘要： The present disclosure provides probe cards which may be used for testing microelectronic components, including methods of making and using such probe cards. One exemplary implementation provides a probe card that employs a substrate with a plurality of openings. A first probe, which may be used to contact a microelectronic component, includes a first conductor slidably received in one of the openings and a first electrical trace. The electrical trace may be patterned from a metal layer on the back of the substrate and include a resilient free length adapted to urge the first conductor to extend outwardly beyond the front of the substrate. A second probe includes a second conductor slidably received in another one of the openings and a second electrical trace. The second electrical trace may be patterned from a metal layer on the front of the substrate and include a resilient free length adapted to urge the second conductor to extend outwardly beyond the back of the substrate. An electrical pathway through the substrate may electrically couple and first and second electrical traces.
摘要翻译：本公开提供了可用于测试微电子部件的探针卡，包括制造和使用这种探针卡的方法。一个示例性实施例提供了采用具有多个开口的基板的探针卡。可用于接触微电子部件的第一探针包括可滑动地容纳在一个开口中的第一导体和第一电迹线。电迹线可以从衬底的背面上的金属层图案化，并且包括适于促使第一导体向外延伸超出衬底前部的弹性自由长度。第二探针包括可滑动地容纳在另一个开口中的第二导体和第二电迹线。第二电迹线可以从衬底前面的金属层图案化，并且包括适于促使第二导体向外延伸超过衬底背面的弹性自由长度。穿过衬底的电路可以电耦合和第一和第二电迹线。

96. 发明申请

US20050046038A1 Multi-dice chip scale semiconductor components 有权
标题翻译：多芯片尺寸半导体元件
公开(公告)号：US20050046038A1
公开(公告)日：2005-03-03
申请号：US10962931
申请日：2004-10-11
申请人： Warren Farnworth , Alan Wood , William Hiatt , James Wark , David Hembree , Kyle Kirby , Pete Benson
发明人： Warren Farnworth , Alan Wood , William Hiatt , James Wark , David Hembree , Kyle Kirby , Pete Benson
IPC分类号： H01L21/56 , H01L21/60 , H01L21/768 , H01L21/98 , H01L23/31 , H01L23/48 , H01L25/065 , G01R31/02
CPC分类号： H01L21/561 , B33Y70/00 , B33Y80/00 , H01L21/563 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05111 , H01L2224/05118 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05178 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05559 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05664 , H01L2224/05666 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/16145 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/351 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.
摘要翻译：半导体部件包括基模和层叠在基模上的二次模。基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板终端接触。一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

97. 发明授权

US08366852B2 Method of forming temporary carrier structure and associated release techniques 有权
标题翻译：形成临时载体结构和相关释放技术的方法
公开(公告)号：US08366852B2
公开(公告)日：2013-02-05
申请号：US13093672
申请日：2011-04-25
申请人： Kyle Kirby
发明人： Kyle Kirby
IPC分类号： B32B37/00
CPC分类号： H01L21/6835 , H01L2221/68318 , Y10T156/1064 , Y10T156/1082 , Y10T156/1111
摘要： A method of forming a temporary carrier structure is disclosed which includes forming a plurality of recesses in a carrier structure, the recesses extending to a depth that is less than a thickness of the carrier structure, forming a dissolvable material in the recesses and above a first surface of the carrier structure, securing a thin substrate above the first surface of the carrier structure using the dissolvable material to secure the thin substrate in place, performing at least one process operation on a second surface of the carrier structure to expose the dissolvable material in the recesses and contacting the exposed dissolvable material with a release agent so as to dissolve at least a portion of the dissolvable material.
摘要翻译：公开了一种形成临时载体结构的方法，其包括在载体结构中形成多个凹部，所述凹部延伸到小于载体结构的厚度的深度，在凹部中形成可溶解材料，并且在第一载体结构的表面，使用可溶解材料将薄衬底固定在载体结构的第一表面上，以将薄衬底固定就位，在载体结构的第二表面上进行至少一个工艺操作以将可溶解材料暴露在所述凹部和暴露的可溶解材料与脱模剂接触以溶解至少一部分可溶解材料。

98. 发明申请

US20110284152A1 METHOD OF FORMING TEMPORARY CARRIER STRUCTURE AND ASSOCIATED RELEASE TECHNIQUES 有权
标题翻译：形成临时载体结构和相关释放技术的方法
公开(公告)号：US20110284152A1
公开(公告)日：2011-11-24
申请号：US13093672
申请日：2011-04-25
申请人： Kyle Kirby
发明人： Kyle Kirby
IPC分类号： B32B38/10
CPC分类号： H01L21/6835 , H01L2221/68318 , Y10T156/1064 , Y10T156/1082 , Y10T156/1111
摘要： A method of forming a temporary carrier structure is disclosed which includes forming a plurality of recesses in a carrier structure, the recesses extending to a depth that is less than a thickness of the carrier structure, forming a dissolvable material in the recesses and above a first surface of the carrier structure, securing a thin substrate above the first surface of the carrier structure using the dissolvable material to secure the thin substrate in place, performing at least one process operation on a second surface of the carrier structure to expose the dissolvable material in the recesses and contacting the exposed dissolvable material with a release agent so as to dissolve at least a portion of the dissolvable material.
摘要翻译：公开了一种形成临时载体结构的方法，其包括在载体结构中形成多个凹部，所述凹部延伸到小于载体结构的厚度的深度，在凹部中形成可溶解材料，并且在第一载体结构的表面，使用可溶解材料将薄衬底固定在载体结构的第一表面上，以将薄衬底固定就位，在载体结构的第二表面上进行至少一个工艺操作以将可溶解材料暴露在所述凹部和暴露的可溶解材料与脱模剂接触以溶解至少一部分可溶解材料。

99. 发明申请

US20110233777A1 THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS 失效
标题翻译：用于光电子和存储器波形的通过波形互连
公开(公告)号：US20110233777A1
公开(公告)日：2011-09-29
申请号：US13154550
申请日：2011-06-07
申请人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
发明人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译：公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

100. 发明授权

US07955946B2 Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices 有权
标题翻译：确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件
公开(公告)号：US07955946B2
公开(公告)日：2011-06-07
申请号：US11439078
申请日：2006-05-22
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L21/76
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法和半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

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