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    • 92. 发明申请
    • TECHNIQUES FOR FAST AREA-EFFICIENT INCREMENTAL PHYSICAL SYNTHESIS
    • 用于快速增强体力合成的技术
    • US20100257499A1
    • 2010-10-07
    • US12416960
    • 2009-04-02
    • Charles J. AlpertZhuo LiChin Ngai SzeLouise H. TrevillyanYing Zhou
    • Charles J. AlpertZhuo LiChin Ngai SzeLouise H. TrevillyanYing Zhou
    • G06F17/50
    • G06F17/5068
    • A fast technique for circuit optimization in a physical synthesis flow iteratively repeats slew-driven (timerless) buffering and repowering with a changing slew target. Buffers are added as necessary with each iteration to bring the nets in line with the new slew target, but any nets having positive slack from the previous iteration are skipped, and that slack information is cached for future timing analysis. Buffer insertion is iteratively repeated with incrementally decreasing slew until a minimum slew is reached, or when none of the nets have negative slack. Iteratively repeating the timerless buffering and repowering while gradually decreasing the slew constraint in this manner results in a design structure which retains high quality of results with significantly smaller area and wire length, and with only a small computational overhead.
    • 物理合成流中电路优化的快速技术可以迭代地重复使用转换驱动(定时器)缓冲并使用更改的转换目标重新启动。 根据需要,每次迭代添加缓冲区,使网格与新的转换目标一致,但是跳过与上一次迭代相反的任何网络,并且缓存信息被缓存以便将来进行时序分析。 缓冲区插入被迭代重复,逐渐减小,直到达到最小的转差,或者当没有网络有负的松弛时。 以这种方式迭代地重复定时器缓冲和重新赋能,同时以这种方式逐渐减小摆动约束导致设计结构,其保持高质量的结果,具有明显更小的面积和导线长度,并且仅具有小的计算开销。