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91. 发明授权

US09960939B1 Transmitter and method for transmitting a bluetooth packet 有权
公开(公告)号：US09960939B1
公开(公告)日：2018-05-01
申请号：US15590833
申请日：2017-05-09
申请人： Beken Corporation
发明人： Yiming Huang , Weifeng Wang
IPC分类号： H04L7/033 , H04L27/12 , H04L27/20 , H04B1/04
CPC分类号： H04L27/12 , H04B2001/0408 , H04L7/0331 , H04L27/2017
摘要： Embodiments discloses a transmitter for transmitting a Bluetooth packet in an enhanced data rate format. The Bluetooth packet includes a GFSK modulated segment, a Guard segment and a DPSK modulated segment. The transmitter comprises a first multiplexer configured to select a phase signal from a Guard phase signal, a received GFSK phase signal and a received DPSK phase signal based on time; a second multiplexer configured to select a amplitude signal from a Guard amplitude signal, a received GFSK amplitude signal and a received DPSK amplitude signal based on time, a phase to frequency converter communicatively coupled to the first multiplexer and configured to convert the selected phase signal into converted frequency signal. The transmitter further comprises a phase lock loop, a digital to analog converter and a power amplifier.

92. 发明授权

US09831984B1 Method and device for error decision 有权
公开(公告)号：US09831984B1
公开(公告)日：2017-11-28
申请号：US15164892
申请日：2016-05-26
申请人： Beken Corporation
发明人： Lianxue Liu , Donghui Gao , Weifeng Wang
IPC分类号： H03M13/00 , H04L1/00 , H04W4/00
CPC分类号： H04L1/0045 , H04L1/0061 , H04L1/0065 , H04L1/0072 , H04L1/08
摘要： A method of error decision, comprising: for each of a plurality of demodulated decision information in a codeword, identifying by a controller, a decoded bit for the demodulated decision as an erasable error bit if the demodulated decision information is larger than a first threshold and smaller than a second threshold; for all the identified erasable error bits, enumerating by a calculator, all possible combinations of the identified erasable error bits; for each combination of all enumerated possible combinations feeding by the calculator, each combination with all other decided decoded bits of the code word into a header correction checker; performing, by the header correction checker, header correction checking for each combination; and outputting, by a decision circuit connected to the header correction checker, a combination with a correct header correction check (HEC) result as an output sequence.

93. 发明申请

US20170054206A1 ANTENNA AND METHOD OF FORMING THE ANTENNA 有权
标题翻译：天线和形成天线的方法
公开(公告)号：US20170054206A1
公开(公告)日：2017-02-23
申请号：US14849579
申请日：2015-09-09
申请人： Beken Corporation
发明人： Bo Jia , Lizhen Zhu , Qunshan Xu
IPC分类号： H01Q1/38
CPC分类号： H01Q1/38 , H01Q1/36
摘要： The invention discloses an antenna comprising a plurality of laminated layers of radiating elements, wherein each layer of radiating elements is arranged in a zigzag pattern; a feed point connected to one of the plurality laminated layers of the radiating elements and is configured to receive a radio frequency signal; and a plated via configured to couple the plurality of laminated layers of radiating elements; wherein the radiating elements are configured to radiate the radio frequency signal.
摘要翻译：本发明公开了一种天线，包括多个辐射元件叠层，其中每层辐射元件以锯齿形图案布置; 连接到所述辐射元件的所述多个层叠层之一的馈电点，并且被配置为接收射频信号; 以及电镀通孔，被配置为耦合所述辐射元件的所述多个叠层; 其中所述辐射元件被配置为辐射所述射频信号。

94. 发明授权

US09431964B2 Operational amplifier and method of operating the operational amplifier 有权
标题翻译：运算放大器和运算放大器的操作方法
公开(公告)号：US09431964B2
公开(公告)日：2016-08-30
申请号：US14585190
申请日：2014-12-30
申请人： Beken Corporation
发明人： Jiazhou Liu , Dawei Guo
IPC分类号： H03F3/45 , H03F1/02 , H03F3/217 , H03F3/21
CPC分类号： H03F1/0205 , H03F1/0277 , H03F3/211 , H03F3/2171 , H03F3/45179 , H03F3/4521 , H03F2203/21109 , H03F2203/45116 , H03F2203/45288
摘要： An operational amplifier comprises a first input pair, a second input pair, a switch and a first current mirror. The first input pair comprises a different type of MOS transistor from the second input pair. The switch determines which one of the first or the second input pair is functioning and the operating input pair is configured to output voltage. The switch is further connected to the first input pair and the first current mirror. The first current mirror is further connected to the second input pair, and is configured to copy a current passing through the switch to the second input pair. Therefore an increase of transconductance of the first input pair is compensated by a decrease of transconductance of the second input pair, and the operational amplifier has a substantially constant transconductance no matter which of the first input pair and the second input pair is functioning.
摘要翻译：运算放大器包括第一输入对，第二输入对，开关和第一电流镜。第一输入对包括与第二输入对不同类型的MOS晶体管。开关确定第一或第二输入对中哪一个正在工作，并且操作输入对配置为输出电压。开关进一步连接到第一输入对和第一电流镜。第一电流镜还连接到第二输入对，并且被配置为将通过开关的电流复制到第二输入对。因此，无论第一输入对和第二输入对中哪一个如何工作，第一输入对的跨导的增加被第二输入对的跨导的减小补偿，并且运算放大器具有基本上恒定的跨导。

95. 发明授权

US09344048B1 Operational amplifier and method of amplifying with the operational amplifier 有权
标题翻译：运算放大器和运算放大器的放大方法
公开(公告)号：US09344048B1
公开(公告)日：2016-05-17
申请号：US14634890
申请日：2015-03-01
申请人： Beken Corporation
发明人： Jiazhou Liu , Dawei Guo
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/4565 , H03F3/45659 , H03F2200/153 , H03F2203/45072 , H03F2203/45074 , H03F2203/45264 , H03F2203/45418
摘要： An operational amplifier comprises an input pair, an aiding unit, an even number of amplification stages, a feeding unit, a first current source, a second current source. Both the input pair and the aiding unit are connected to the first current source. The input pair receives differential input voltage. Both the input pair and the aiding unit are further connected to a first stage of the even number of amplification stages. The even number of amplification stages are connected in series, and the last stage of the amplification stages outputs differential output voltages. The feeding unit is configured to receive a common mode voltage of the differential output voltages, and feeds a voltage on a first node of the feeding unit back to the aiding unit so as to provide bias voltage to the aiding unit. The aiding unit avoids dead lock of the input pair.
摘要翻译：运算放大器包括输入对，辅助单元，偶数个放大级，馈电单元，第一电流源，第二电流源。输入对和辅助单元都连接到第一电流源。输入对接收差分输入电压。输入对和辅助单元都进一步连接到偶数个放大级的第一级。放大级的偶数个串联，放大级的最后阶段输出差分输出电压。馈送单元被配置为接收差分输出电压的共模电压，并且将馈电单元的第一节点上的电压馈送到辅助单元，以便向辅助单元提供偏置电压。辅助单元避免输入对的死锁。

96. 发明授权

US09197228B2 Circuit and method for adjusting oscillating frequency of an oscillator 有权
标题翻译：用于调整振荡器振荡频率的电路和方法
公开(公告)号：US09197228B2
公开(公告)日：2015-11-24
申请号：US14270377
申请日：2014-05-06
申请人： Beken Corporation
发明人： Ronghui Kong , Dawei Guo
IPC分类号： H03B5/08 , H03L7/181 , H03L7/18 , H03B1/00 , H03K3/03
CPC分类号： H03L7/181 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03K3/0315 , H03L7/099 , H03L7/0995 , H03L7/18
摘要： A circuit comprises an oscillator, a frequency divider and a comparator. The oscillator generates an oscillating signal (Fvco). The frequency divider is communicatively coupled to the oscillator, divides a frequency of the oscillating signal by a denominator and generates a divided signal. The comparator is communicatively coupled to the oscillator and the frequency divider, and is configured to obtain a first count of the divided signal (Fvco/N) within a predetermined time and a second count of a reference signal within the predetermined time; compare the first count with the second count, and generate a comparison result according to the first count and the second count. The oscillator is further configured to adjust the frequency of the oscillating signal according to the comparison result.
摘要翻译：电路包括振荡器，分频器和比较器。振荡器产生振荡信号（Fvco）。分频器通信地耦合到振荡器，将振荡信号的频率除以分母，并产生分频信号。比较器通信地耦合到振荡器和分频器，并且被配置为在预定时间内获得分频信号的第一计数（Fvco / N）和在预定时间内的参考信号的第二计数; 将第一计数与第二计数进行比较，并根据第一计数和第二计数生成比较结果。振荡器还被配置为根据比较结果来调节振荡信号的频率。

97. 发明申请

US20150042391A1 Calibration Circuit and Method 有权
标题翻译：校准电路和方法
公开(公告)号：US20150042391A1
公开(公告)日：2015-02-12
申请号：US14191440
申请日：2014-02-27
申请人： Beken Corporation
发明人： Dawei Guo , Jianqin Zheng
IPC分类号： H03H11/22
CPC分类号： H03H7/48
摘要： A circuit comprises a phase combiner and four output ports. The phase combiner adds an in-phase positive input and a quadrature positive input to obtain an in-phase positive output, adds an in-phase negative input and a quadrature negative input to obtain an in-phase negative output, adds the in-phase negative input and the quadrature positive input to obtain a quadrature positive output, and adds the in-phase positive input and the quadrature negative input to obtain a quadrature negative output. The four output ports, are respectively configured to output the in-phase positive output, the in-phase negative output, the quadrature positive output, and the quadrature negative output.
摘要翻译：电路包括相位合成器和四个输出端口。相位合成器加上同相正输入和正交正输入以获得同相正输出，相加负输入和正交负输入以获得同相负输出，将同相相加负输入和正交正输入以获得正交正输出，并且将同相正输入和正交负输入相加以获得正交负输出。四个输出端口分别配置为输出同相正输出，同相负输出，正交正输出和正交负输出。

98. 发明授权

US08730061B2 Method for calibrating an on-board unit and a test device, a method for wireless toll collection 有权
标题翻译：用于校准车载单元和测试设备的方法，用于无线收费的方法
公开(公告)号：US08730061B2
公开(公告)日：2014-05-20
申请号：US12981526
申请日：2010-12-30
申请人： Yanfeng Wang , Dawei Guo , Jiazhou Liu
发明人： Yanfeng Wang , Dawei Guo , Jiazhou Liu
IPC分类号： G08G1/00 , G08G1/01 , G07B15/02 , H04B1/40 , H04B7/00
CPC分类号： G07B15/063
摘要： A method comprises: disposing an on-board unit at a preset relative position with respect to a road-side unit; transmitting a signal by the road-side unit; receiving the signal by the on-board unit and detecting a strength of the received signal; calculating, by the on-board unit, a calculated strength of the received signal according to the detected strength of the received signal; storing the calculated strength of the received signal in a memory accessible by the on-board unit; using the stored calculated strength of the received signal to determine if payment of a toll should be made.
摘要翻译：一种方法包括：将车载单元布置在相对于路侧单元的预设相对位置处; 通过路侧单元发送信号; 通过机载单元接收信号并检测接收信号的强度; 根据检测到的接收信号的强度，由车载单元计算接收信号的计算强度; 将计算出的接收信号的强度存储在由板上单元访问的存储器中; 使用存储的所计算的接收信号的强度来确定是否应该支付费用。

99. 发明授权

US08594237B2 GFSK modulator and a method for reducing residual frequency modulation and a digital enhanced cordless telecommunication transmitter including the GFSK modulator 有权
标题翻译： GFSK调制器和减少残余频率调制的方法以及包括GFSK调制器的数字增强型无绳电信发射机
公开(公告)号：US08594237B2
公开(公告)日：2013-11-26
申请号：US12981518
申请日：2010-12-30
申请人： Yiming Huang , Ronghui Kong , Caogang Yu
发明人： Yiming Huang , Ronghui Kong , Caogang Yu
IPC分类号： H03K7/06
CPC分类号： H03C3/04 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C2200/0079
摘要： A GFSK modulator comprises: a first compensation module, configured to receive a GFSK pulse signal, apply a first amplitude compensation and a first delay compensation to the GFSK pulse signal, so as to generate a first compensated control signal; a second compensation module, configured to receive the GFSK pulse signal, apply a second amplitude compensation and a second delay compensation to the GFSK pulse signal, so as to generate a second compensated control signal; a closed-loop PLL module including a closed-loop PLL, configured to receive and use the first and the second compensated control signals to generate a modulated signal.
摘要翻译： GFSK调制器包括：第一补偿模块，被配置为接收GFSK脉冲信号，对GFSK脉冲信号施加第一幅度补偿和第一延迟补偿，以产生第一补偿控制信号; 第二补偿模块，被配置为接收所述GFSK脉冲信号，对所述GFSK脉冲信号施加第二幅度补偿和第二延迟补偿，以产生第二补偿控制信号; 包括闭环PLL的闭环PLL模块，被配置为接收和使用第一和第二补偿控制信号以产生调制信号。

100. 发明授权

US08339168B2 Pulse-width modulation circuit, a device including the same and a method for pulse-width modulation 有权
标题翻译：脉宽调制电路，包括该脉冲宽度调制电路的装置和脉冲宽度调制方法
公开(公告)号：US08339168B2
公开(公告)日：2012-12-25
申请号：US12987161
申请日：2011-01-10
申请人： Yunbin Tao
发明人： Yunbin Tao
IPC分类号： H03K3/017
CPC分类号： H03K7/08
摘要： A PWM circuit comprises: a charge and discharge circuit to receive a initial signal and, according to the initial signal, increase a voltage at an output end of thereof linearly or decrease the voltage; a comparator with a positive input end to receive a control signal and a negative input end connected to the output end of the charge and discharge circuit; a voltage transmission circuit with a first input end to receive the initial signal and a second input end to receive an output of the comparator, the voltage transmission circuit is configured to transmit the initial signal to an output end of the voltage transmission circuit when the output of the comparator is digital 1, and output digital 0 when the output of the comparator is digital 0.
摘要翻译： PWM电路包括：充电和放电电路，用于接收初始信号，并且根据初始信号线性地增加其输出端处的电压或降低电压; 具有正输入端以接收控制信号的比较器和连接到充放电电路的输出端的负输入端; 具有第一输入端以接收初始信号的电压传输电路和用于接收比较器的输出的第二输入端，所述电压传输电路被配置为当所述输出端子的输出端将所述初始信号发送到所述电压传输电路的输出端的比较器是数字1，当比较器的输出为数字0时，输出数字0。

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