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1. 发明授权

US11249509B2 Adaptive voltage converter 有权
公开(公告)号：US11249509B2
公开(公告)日：2022-02-15
申请号：US16993231
申请日：2020-08-13
申请人： AMBIQ MICRO, INC.
发明人： Scott Hanson
IPC分类号： H03L7/18 , G06F1/06 , H03L7/06 , H03L7/181 , G06F1/3237 , G06F1/3287 , G06F1/12 , G06F11/30 , G06F11/34 , G06F13/10 , G01R19/00 , G05F1/56 , H03K17/687 , H03M1/12 , H03L7/00 , G05F1/575 , G06F1/3296 , H02M3/158 , H02M1/00
摘要： An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

2. 发明授权

US11133809B2 Method and circuit for determining phase continuity of a local oscillator signal, and local oscillator signal generation circuit 有权
公开(公告)号：US11133809B2
公开(公告)日：2021-09-28
申请号：US16641244
申请日：2017-09-28
申请人： Intel IP Corporation
发明人： Stefan Tertinek
IPC分类号： H03L7/099 , H03L7/091 , H03L7/181 , H03L7/185 , H04B1/403
摘要： A method for determining phase continuity of a local oscillator signal generated using a frequency divider is provided. The method includes determining at least one sample of the local oscillator signal. Further, the method includes determining information on the phase continuity using the at least one sample.

3. 发明授权

US11042180B1 Detecting irregularities in an input clock signal 有权
公开(公告)号：US11042180B1
公开(公告)日：2021-06-22
申请号：US16825027
申请日：2020-03-20
申请人： Arm Limited
发明人： Ivan Michael Lowe , Mikael Yves Marie Rien
IPC分类号： G06F1/06 , H03L7/181 , G06F1/08
摘要： An apparatus has an input interface for receiving an input clock signal, and a plurality N of clock divider circuits, each clock divider circuit generating a corresponding monitored clock signal by dividing the input clock signal by N. Each clock divider circuit is arranged, when generating a leading edge of each clock cycle of its corresponding monitored clock signal, to use a leading edge of a different clock cycle of the input clock signal to the clock cycle of the input clock signal used by any other of the clock divider circuits. Analysis circuitry provided in association with each clock divider circuit produces a width indication for each clock cycle of the corresponding monitored clock signal. Alarm generation circuitry then triggers an alarm signal when, for any of the monitored clock signals, a variation in the width indication is detected over multiple clock cycles of that monitored clock signal.

4. 发明申请

US20200371544A1 ADAPTIVE VOLTAGE CONVERTER 审中-公开
公开(公告)号：US20200371544A1
公开(公告)日：2020-11-26
申请号：US16993231
申请日：2020-08-13
申请人： AMBIQ MICRO, INC.
发明人： Scott Hanson
IPC分类号： G06F1/06 , H03L7/18 , H03L7/06 , H03L7/181 , G06F1/3237 , G06F1/3287 , G06F1/12 , G06F11/30 , G06F11/34 , G06F13/10 , G01R19/00 , G05F1/56 , H03K17/687 , H03M1/12 , H03L7/00 , G05F1/575 , G06F1/3296 , H02M3/158
摘要： An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

5. 发明授权

US10338632B2 Adaptive voltage converter 有权
公开(公告)号：US10338632B2
公开(公告)日：2019-07-02
申请号：US15516883
申请日：2015-09-15
申请人： Ambiq Micro, Inc. , Scott Hanson , Yanning Lu
发明人： Scott Hanson , Yanning Lu
IPC分类号： H02M1/12 , G06F1/06 , H03L7/18 , H03L7/06 , H03L7/181 , G06F1/12 , G06F11/30 , G06F11/34 , G06F13/10 , G01R19/00 , G05F1/56 , H03K17/687 , H03M1/12 , H03L7/00 , G06F1/3237 , G06F1/3287 , G05F1/575 , G06F1/3296 , H02M3/158 , H02M1/00
摘要： An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

6. 发明申请

US20190179361A1 ADAPTIVE VOLTAGE CONVERTER 审中-公开
公开(公告)号：US20190179361A1
公开(公告)日：2019-06-13
申请号：US16276931
申请日：2019-02-15
申请人： AMBIQ MICRO, INC.
发明人： Scott Hanson
IPC分类号： G06F1/06 , G06F1/3287 , G06F1/3237 , H03L7/18 , H03L7/06 , H03L7/181 , G06F11/30 , G06F11/34 , G01R19/00 , H03K17/687 , G05F1/56 , G06F13/10 , H03L7/00 , H03M1/12 , G06F1/12 , H02M3/158 , G06F1/3296 , G05F1/575
摘要： An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

7. 发明授权

US10193561B2 Phase locked loops 有权
公开(公告)号：US10193561B2
公开(公告)日：2019-01-29
申请号：US15384861
申请日：2016-12-20
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： John Paul Lesso
IPC分类号： H03L7/06 , H03L7/091 , H03L7/099 , H03L7/181 , H03L7/085 , H03L7/089
摘要： This application relates to methods and apparatus for phase locked loops. A phase-and-frequency detector (101) receives a reference clock signal (CKref) and a feedback signal (SFB) and outputs a first adjustment signal (U) that is modulated between respective first and second signal levels to provide control pulses indicating that an increase in frequency required for phase and frequency lock, and a second adjustment signal (D) that is modulated between respective first and second signal levels to provide control pulses indicating that a decrease in frequency required for phase and frequency lock. First and second time-to-digital converters (201-1 and 201-2) receive the first and second adjustment signals respectively and output respective first and second digital signals indicative of the duration of said control pulses. Each time-to-digital converter comprises a controlled-oscillator (401, 801) configured so as to operate at a first frequency when the respective adjustment signal is at the first signal level and operate at a second frequency when the respective adjustment signal is at the second signal level and a counter (403) configured to produce a count value of the number oscillations of the controlled-oscillator in each of a succession of count periods defined by a count clock signal. The first and second digital signals are based on the count values output from the respective counters. The difference between the first and second digital signals may be determined and input to digital loop filter (203) before driving numerically-controlled-oscillator (204) to produce the output signal.

8. 发明授权

US10171094B2 High accuracy clock synchronization circuit 有权
公开(公告)号：US10171094B2
公开(公告)日：2019-01-01
申请号：US15492573
申请日：2017-04-20
申请人： SEIKO EPSON CORPORATION
发明人： Katsuhito Nakajima
IPC分类号： H03L7/095 , H03L7/099 , H03L7/181
摘要： A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a signal process on frequency control data based on a result of the phase comparison, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of frequency control data having undergone the signal process. The phase comparator includes a counter that performs a count operation by using the input signal, and performs the phase comparison by comparing a count value in the counter inn (where n is an integer of 2 or more) cycles of the reference signal with an expected value of the count value in integers.

9. 发明授权

US09941865B2 Method and circuitry for generating trigger signal and associated non-transitory computer program product 有权
公开(公告)号：US09941865B2
公开(公告)日：2018-04-10
申请号：US14992057
申请日：2016-01-11
申请人： MEDIATEK Inc.
发明人： Keng-Jan Hsiao , Wen-Chi Chao , Sheng-Chu Wu , Cheng-Yu Chien
IPC分类号： H03B5/32 , H03K3/0231 , H03L7/181 , H03L7/08 , H03B5/36 , H03L1/00
CPC分类号： H03K3/02315 , H03B5/36 , H03L1/00 , H03L7/08 , H03L7/181
摘要： A method and circuitry for generating a trigger signal based on an oscillation signal and associated non-transitory computer program product are provided. The method includes following steps. Firstly, a calibration value is obtained according to a reference frequency and a frequency of the oscillation signal, and a counting value is gradually altered from a first initial value to a breakpoint value. Secondly, the counting value is updated to a second initial value when the counting value is equal to the breakpoint value. Then, the counting value is gradually altered from the second initial value to a final value, and the trigger signal is generated when the counting value is equal to the final value.

10. 发明授权

US09762220B2 Frequency synthesizer and method controlling frequency synthesizer 有权
公开(公告)号：US09762220B2
公开(公告)日：2017-09-12
申请号：US14974333
申请日：2015-12-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sang-Wook Han , Sung-Jun Lee , Joon-Hee Lee , Jong-Won Choi
IPC分类号： H03K3/03 , H03K7/08 , H03K5/131 , H03L7/083 , H03L7/181 , H03L7/10 , H03L7/197 , H03K5/00
CPC分类号： H03K5/131 , H03K2005/00071 , H03K2005/00273 , H03L7/083 , H03L7/102 , H03L7/181 , H03L7/1974 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

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