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1. 发明申请

US20170371990A1 MODEL-BASED CALIBRATION OF AN ALL-DIGITAL PHASE LOCKED LOOP 审中-公开
公开(公告)号：US20170371990A1
公开(公告)日：2017-12-28
申请号：US15192278
申请日：2016-06-24
申请人： QUALCOMM Incorporated
发明人： Magnus Olov WIKLUND , Emanuele LOPELLI , Charles WANG
IPC分类号： G06F17/50 , H04W88/02 , H03L7/093 , H03L7/099
CPC分类号： G06F17/5036 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03C3/0991 , H03L7/093 , H03L7/0991 , H03L2207/12 , H03L2207/50 , H04W88/02
摘要： A method of calibrating an All-Digital Phase Locked Loop (ADPLL) includes obtaining a model of the ADPLL and applying an input signal to both the ADPLL and to the model. The ADPLL generates an actual output of the ADPLL, while the model generates a model output. An error between the actual output of the ADPLL and the model output is then sensed. The method also includes generating a calibration value based on the error between the actual output of the ADPLL and the model output, and adjusting a feedforward gain of the ADPLL based on the calibration value.

2. 发明申请

US20170222794A1 TRIM FOR DUAL-PORT FREQUENCY MODULATION 有权
公开(公告)号：US20170222794A1
公开(公告)日：2017-08-03
申请号：US15493229
申请日：2017-04-21
申请人： SUNRISE MICRO DEVICES, INC.
发明人： Mario LAFUENTE , Paul Edward GORDAY
IPC分类号： H04L7/033 , H04L27/12
CPC分类号： H04L7/033 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0991 , H04L7/0331 , H04L27/0014 , H04L27/10 , H04L27/12 , H04L27/127 , H04L27/152 , H04L27/3411 , H04L43/50 , H04L2027/0055
摘要： Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

3. 发明申请

US20170207906A1 TWO POINT POLAR MODULATOR 有权
公开(公告)号：US20170207906A1
公开(公告)日：2017-07-20
申请号：US14996017
申请日：2016-01-14
申请人： FRONTIER MICROSYSTEMS LIMITED
发明人： Mark DAWKINS
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0331 , H03C3/0916 , H03C3/0941 , H03C3/0958 , H03C3/0975 , H03C5/00 , H04L7/0091 , H04L27/00
摘要： A two-point phase modulator comprising a phase locked loop, PLL, having a voltage controlled oscillator, VCO, and a feedback path, a first modulation circuit for introducing a first modulation signal into the feedback path, the first modulation circuit generating the first modulation signal using a reference clock signal extracted from the PLL and derived from a first clock, a second modulation circuit for introducing a second modulation input into the VCO, the second modulation circuit generating the second modulation signal using a clock signal generated independently of the reference clock and a synchronizer for aligning the second modulation signal in time with the first clock signal.

4. 发明申请

US20170005853A1 TRIM FOR DUAL-PORT FREQUENCY MODULATION 有权
标题翻译：双端口频率调制TRIM
公开(公告)号：US20170005853A1
公开(公告)日：2017-01-05
申请号：US15007969
申请日：2016-01-27
申请人： SUNRISE MICRO DEVICES, INC.
发明人： Mario LAFUENTE , Paul Edward GORDAY
IPC分类号： H04L27/34 , H04L12/26 , H04L7/033
CPC分类号： H04L7/033 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0991 , H04L7/0331 , H04L27/0014 , H04L27/10 , H04L27/12 , H04L27/127 , H04L27/152 , H04L27/3411 , H04L43/50 , H04L2027/0055
摘要： Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.
摘要翻译：各种方法提供了在无线电收发器的双端口锁相环（PLL）中调整增益。使用无线电解调器进行调制精度测量，从而降低外部测试设备的成本和复杂性。

5. 发明申请

US20160248430A1 PHASE LOCKED LOOP HAVING FRACTIONAL VCO MODULATION 有权
标题翻译：具有相应的VCO调制的相位锁定环
公开(公告)号：US20160248430A1
公开(公告)日：2016-08-25
申请号：US14631305
申请日：2015-02-25
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： KHURRAM WAHEED , KEVIN B. TRAYLOR
IPC分类号： H03L7/099 , H03M3/00 , H03M7/16 , H03L7/081 , H03B5/12
CPC分类号： H03L7/099 , H03B5/124 , H03B5/1265 , H03C3/00 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0975 , H03L7/081 , H03L7/197 , H03M3/422 , H03M7/165
摘要： An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.
摘要翻译：集成电路包括双端口调制器和压控振荡器（VCO）。双端口调制器具有用于接收发射机调制信号的第一输入端，用于提供高端口调制信号的分数部分的第一输出端，用于提供高端口调制信号的整数部分的第二输出端和用于提供低端口调制信号。 VCO耦合到双端口调制器，并且具有用于接收高端口调制信号的小数部分的第一输入端，用于接收高端口调制信号的整数部分的第二输入端，用于接收调谐信号的第三输入端在低端口调制信号上，以及第一输出端用于输出RF信号。双端口调制器提供用于产生高端口调制信号的小数部分的带符号单位信号。

6. 发明申请

US20160238998A1 TIME TO DIGITAL CONVERTER AND PHASE LOCKED LOOP 审中-公开
标题翻译：数字转换器和相位锁定环路
公开(公告)号：US20160238998A1
公开(公告)日：2016-08-18
申请号：US15041202
申请日：2016-02-11
申请人： NXP B.V.
发明人： Nenad Pavlovic , Vladislav Dyachenko , Tarik Saric
IPC分类号： G04F10/00 , H03L7/099 , H03L7/197 , H03M1/38
CPC分类号： G04F10/005 , G01S7/02 , G01S7/35 , G01S13/32 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03L7/085 , H03L7/0992 , H03L7/1974 , H03L7/1976 , H03M1/38
摘要： A time to digital converter (10) is disclosed. The time to digital converter (10) comprises: a synchronisation block (20) configured to output a voltage pulse (110) with duration based on a time difference between a reference oscillating signal (101) and an input oscillating signal (107); a charge pump (41) arranged to receive the voltage pulse (110) and to convert the voltage pulse into a current pulse; an integrator (50) comprising an integrator capacitor (24, 25), the integrator (50) being configured to receive the current pulse (110) and integrate the current pulse (110) as a charge on the integrator capacitor (24, 25), resulting in an integrator output voltage (115); and a successive approximation register (40) configured to determine the integrator output voltage (115) with respect to a reference voltage by adjusting the charge on the integrator capacitor (24, 25) so as to reduce the integrator output voltage (115) to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage (115) as a digital signal (125). A phase locked loop comprising the time to digital converter (10) is disclosed.
摘要翻译：公开了一种数字转换器（10）。数字转换器（10）的时间包括：同步块（20），被配置为基于参考振荡信号（101）和输入振荡信号（107）之间的时间差输出具有持续时间的电压脉冲（110）; 布置成接收电压脉冲（110）并将电压脉冲转换成电流脉冲的电荷泵（41）; 积分器（50），包括积分器电容器（24,25），所述积分器（50）被配置为接收所述电流脉冲（110）并且将所述电流脉冲（110）作为所述积分器电容器（24,25）上的电荷进行积分，，导致积分器输出电压（115）; 以及逐次逼近寄存器（40），被配置为通过调整积分电容器（24,25）上的电荷来确定相对于参考电压的积分器输出电压（115），以便将积分器输出电压（115）减小到通过逐次逼近的参考电压的最低有效位（D0），并且被配置为输出所确定的积分器输出电压（115）作为数字信号（125）。公开了一种包括时间到数字转换器（10）的锁相环。

7. 发明授权

US08693959B1 System and apparatus for a direct conversion receiver and transmitter 有权
标题翻译：用于直接转换接收机和发射机的系统和设备
公开(公告)号：US08693959B1
公开(公告)日：2014-04-08
申请号：US09621407
申请日：2000-07-21
申请人： William J. Domino , Scott A. Griffith , Dmitriy Rozenblit
发明人： William J. Domino , Scott A. Griffith , Dmitriy Rozenblit
IPC分类号： H04B1/40
CPC分类号： H03C3/0966 , H03C3/0941 , H03C3/0958 , H03D3/007 , H04B1/30 , H04B1/408 , H04L27/20
摘要： A system for transmitting and receiving data is provided. The system includes a direct-conversion receiver that receives a signal modulated on a carrier frequency signal. The direct-conversion receiver includes one or more subharmonic local oscillator mixers. A local oscillator is connected to the direct conversion receiver, and generates a signal having a frequency equal to a subharmonic of the carrier frequency signal. A transmitter is connected to the local oscillator, which uses the local oscillator signal to transmit outgoing data.
摘要翻译：提供了一种用于发送和接收数据的系统。该系统包括接收在载波频率信号上调制的信号的直接转换接收机。直接转换接收器包括一个或多个次谐波本地振荡器混频器。本地振荡器连接到直接转换接收器，并且产生具有等于载波频率信号的次谐波的频率的信号。发送器连接到本地振荡器，其使用本地振荡器信号来发送输出数据。

8. 发明授权

US08634512B2 Two point modulation digital phase locked loop 有权
标题翻译：双点调制数字锁相环
公开(公告)号：US08634512B2
公开(公告)日：2014-01-21
申请号：US13023369
申请日：2011-02-08
申请人： Lai Kan Leung , Chiewcharn Narathong
发明人： Lai Kan Leung , Chiewcharn Narathong
IPC分类号： H03D3/24
CPC分类号： H04L27/20 , H03C3/0941 , H03C3/095 , H03C3/0975
摘要： A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.
摘要翻译：公开了一种双点调制数字锁相环电路。电路包括可在多个频率之间切换的采样时钟输入。电路还包括接收低通调制数据的反馈路径中的Σ-Δ调制器。该电路还包括接收高通调制数据的电压模式数模转换器（VDAC）。该电路还包括耦合到反馈路径和VDAC的输出的模拟压控振荡器。电路还包括耦合到反馈路径的相对数字转换器（PDC），采样时钟和环路滤波器。

9. 发明授权

US08588338B2 Driver circuit for driving a power amplifier 有权
标题翻译：用于驱动功率放大器的驱动电路
公开(公告)号：US08588338B2
公开(公告)日：2013-11-19
申请号：US13733380
申请日：2013-01-03
申请人： SiGe Semiconductor (Europe) Limited
发明人： Jeffrey Wojtiuk
IPC分类号： H04L27/20
CPC分类号： H04L27/34 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C5/00 , H03F3/217 , H03F2200/331 , H04L27/361
摘要： A circuit for providing AM/PM modulation is described. The circuit includes a signal generator, which provides two phase modulated (PM) signals used to form two drive signals which are later combined in a constructive/destructive fashion. The combination of the two phase modulated signals form a signal for driving a load. When the load is driven, the resulting signal is AM/PM modulated.
摘要翻译：描述了用于提供AM / PM调制的电路。该电路包括信号发生器，其提供用于形成两个驱动信号的两个相位调制（PM）信号，后者以建设性/破坏性方式组合。两个相位调制信号的组合形成用于驱动负载的信号。当负载被驱动时，所得到的信号被AM / PM调制。

10. 发明授权

US08509373B2 Apparatus and method for generating small-size spread spectrum clock signal 有权
标题翻译：用于产生小尺寸扩频时钟信号的装置和方法
公开(公告)号：US08509373B2
公开(公告)日：2013-08-13
申请号：US12635553
申请日：2009-12-10
申请人： Ha-Jun Jeon , Sang-Seob Kim
发明人： Ha-Jun Jeon , Sang-Seob Kim
IPC分类号： H03D3/24
CPC分类号： H04B1/69 , H03B23/00 , H03C3/0925 , H03C3/0941 , H03C3/095
摘要： An apparatus and method for generating a small-size spread spectrum clock signal that can include generating a reference clock signal by dividing an external clock signal, detecting frequency and phase differences between a reference clock signal and a comparison clock signal as error signals, modulating a controlled voltage corresponding to the current in accordance with a modulation control signal, outputting an oscillation clock signal having a frequency oscillated according to the modulated controlled voltage as a spectrum-spread version of the external clock signal, and generating the comparison clock signal by dividing the oscillation clock signal, and then compensating for the modulation of the controlled voltage in accordance with a demodulation magnitude that is generated for use in compensating for the modulation magnitude.
摘要翻译：一种用于产生小尺寸扩频时钟信号的装置和方法，其可以包括通过划分外部时钟信号产生参考时钟信号，检测基准时钟信号和比较时钟信号之间的频率和相位差作为误差信号，调制根据调制控制信号对应于电流的受控电压，输出具有根据调制控制电压振荡的频率的振荡时钟信号作为外部时钟信号的频谱扩展版本，并通过将振荡时钟信号，然后根据产生用于补偿调制幅度的解调幅度补偿受控电压的调制。

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