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91. 发明授权

US07962758B2 Method and apparatus for processing arbitrary key bit length encryption operations with similar efficiencies 有权
标题翻译：用于处理类似效率的任意密钥位长加密操作的方法和装置
公开(公告)号：US07962758B2
公开(公告)日：2011-06-14
申请号：US12287864
申请日：2008-10-14
申请人： Hafid Zaabab
发明人： Hafid Zaabab
IPC分类号： G06F21/00 , G06F11/30
CPC分类号： G06F7/728
摘要： A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.
摘要翻译：具有多个级的计算装置或系统，例如在管道装置中，具有定时轨道或者导体位于该级的旁边。具有排列成并行子阵列的大量，即数百个级，时钟导体与子阵列一起被蛇形。在单个阶段，排列是在一个阶段中进行的最短的两次计算发生在返回路径中。阵列可分为独立的部分，用于独立处理。

92. 发明授权

US07957173B2 Composite memory having a bridging device for connecting discrete memory devices to a system 有权
标题翻译：具有用于将分立存储器件连接到系统的桥接装置的复合存储器
公开(公告)号：US07957173B2
公开(公告)日：2011-06-07
申请号：US12401963
申请日：2009-03-11
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/00 , G11C5/02 , G11C5/025
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.
摘要翻译：一种复合存储器件，包括分立存储器件和用于响应具有与存储器件不兼容的格式或协议的全局存储器控制信号来控制分立存储器件的桥接器件。分立存储器件可以是对现有或本地存储器控制信号进行响应的商业现成存储器件或定制存储器件。全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。复合存储器件包括包括分立存储器件和桥接器件的半导体管芯的封装的系统，或者可以包括具有封装的分立存储器件的印刷电路板和安装在其上的封装桥接器件。

93. 发明申请

US20110110388A1 METHOD AND APPARATUS FOR REDUCING THE AMPLITUDE MODULATION OF OPTICAL SIGNALS IN EXTERNAL CAVITY LASERS 有权
标题翻译：用于减少外部激光激光器中光信号振幅调制的方法和装置
公开(公告)号：US20110110388A1
公开(公告)日：2011-05-12
申请号：US12936723
申请日：2008-04-11
申请人： Paolo Baroni , Marco De Donno , Anna Ronchi
发明人： Paolo Baroni , Marco De Donno , Anna Ronchi
IPC分类号： H01S3/10
CPC分类号： H01S3/10038 , H01S3/1055 , H01S5/02216 , H01S5/02248 , H01S5/02284 , H01S5/02415 , H01S5/02476 , H01S5/02492 , H01S5/062 , H01S5/06213 , H01S5/06246 , H01S5/06251 , H01S5/0653 , H01S5/0683 , H01S5/10 , H01S5/101 , H01S5/141
摘要： The present invention concerns a laser apparatus (200) comprising an external cavity laser (ECL) in which the optical signal is modulated by an electrical modulation signal with the purpose of modulating in frequency the laser output signal. The modulation in frequency produces in turn a modulation of intensity (power) of the laser output signal, also denoted amplitude modulation (AM). A method is described of control of the AM amplitude of a signal emitted by an ECL that comprises a gain medium (205), a phase element (206) with variable transmissivity induced by the modulation and a spectrally selective optical filter (209) and that selects and keeps the AM amplitude below a certain desired value or minimizes such value. A control method and a laser apparatus (200) are also described in which the reduction of the AM component of the output power is achieved by acting on the gain of the gain medium of the ECL in such way that the variation of transmissivity caused by the modulation applied to a phase element (206) is at least partially compensated by a corresponding variation of the gain current of the gain medium so as to reduce or to minimize the variation of the loop gain of the laser cavity induced by the modulation.
摘要翻译：本发明涉及一种包括外腔激光器（ECL）的激光装置（200），其中光信号由电调制信号调制，目的是在频率上调制激光输出信号。频率调制又产生激光输出信号的强度（功率）的调制，也称为振幅调制（AM）。描述了一种控制由ECL发射的信号的AM幅度的控制，其包括增益介质（205），由调制引起的具有可变透射率的相位元件（206）和光谱选择性滤光器（209），并且选择并保持AM振幅低于一定的期望值或使这个值最小化。还描述了一种控制方法和激光装置（200），其中通过以ECL的增益介质的增益作用于输出功率的AM分量的减小，使得由至少部分地通过增益介质的增益电流的相应变化补偿施加到相位元件（206）的调制，以便减少或最小化由调制引起的激光腔的环路增益的变化。

94. 发明申请

US20110110165A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权
标题翻译：记忆系统中的时钟模式确定
公开(公告)号：US20110110165A1
公开(公告)日：2011-05-12
申请号：US13006005
申请日：2011-01-13
申请人： Peter B. GILLINGHAM , Graham ALLAN
发明人： Peter B. GILLINGHAM , Graham ALLAN
IPC分类号： G11C8/18 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
摘要翻译：描述了用于存储器件的时钟模式配置电路。存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从先前存储器件接收源同步时钟信号的串行模式。根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

95. 发明授权

US07940572B2 NAND flash memory having multiple cell substrates 有权
标题翻译： NAND闪存具有多个单元基板
公开(公告)号：US07940572B2
公开(公告)日：2011-05-10
申请号：US12143285
申请日：2008-06-20
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11524
摘要： A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
摘要翻译：具有连接到页缓冲器的存储器阵列的多个位线的NAND闪存库，其中连接到相同位线的NAND单元串形成在至少两个阱扇区中。在擦除操作期间，至少一个阱区可以选择性地耦合到擦除电压，使得未选择的阱区被禁止接收擦除电压。当井区的面积减小时，每个井区的电容相应减小。因此，当电荷泵电路驱动能力保持不变时，可以获得NAND闪速存储单元相对于单个存储器组的更高速擦除。或者，通过将具有特定面积的阱段与具有降低的驱动能力的电荷泵相匹配来获得对应于单阱存储器组的恒定擦除速度。降低的驱动电容电荷泵将占用较少的半导体芯片面积，从而降低成本。

96. 发明申请

US20110095796A1 PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME 失效
标题翻译：过程，电压，温度独立切换延迟补偿方案
公开(公告)号：US20110095796A1
公开(公告)日：2011-04-28
申请号：US12984163
申请日：2011-01-04
申请人： Gurpreet BHULLAR , Graham ALLAN
发明人： Gurpreet BHULLAR , Graham ALLAN
IPC分类号： H03L7/06
CPC分类号： H03L7/06 , H03L7/0814 , H03L7/0818 , H03L7/089 , H03L7/093
摘要： A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
摘要翻译：一种用于延迟锁定环路的延迟补偿电路，其包括具有精细延迟线的主延迟线，该延迟线包括精细延迟元件和包括粗延迟元件的粗延迟线，该主延迟线由控制器控制，该延迟补偿电路包括：用于对粗略延迟元件进行建模的可调精细延迟，用于将可调节精细延迟控制为与粗略延迟元件基本相同的值的计数器，用于将系统时钟的表示应用于延迟补偿电路的电路以及从计数器向控制器施加精细延迟计数的电路，用于将主延迟线的精细延迟线调整为与主延迟线的粗略延迟元件基本相同的值。

97. 发明授权

US07908429B2 Apparatus and method of page program operation for memory devices with mirror back-up of data 有权
公开(公告)号：US07908429B2
公开(公告)日：2011-03-15
申请号：US12832121
申请日：2010-07-08
申请人： Hong Beom Pyeon , Jin-Ki Kim , HakJune Oh
发明人： Hong Beom Pyeon , Jin-Ki Kim , HakJune Oh
IPC分类号： G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

98. 发明授权

US07889826B2 Process, voltage, temperature independent switched delay compensation scheme 有权
标题翻译：过程，电压，温度独立的开关延迟补偿方案
公开(公告)号：US07889826B2
公开(公告)日：2011-02-15
申请号：US12026813
申请日：2008-02-06
申请人： Gurpreet Bhullar , Graham Allan
发明人： Gurpreet Bhullar , Graham Allan
IPC分类号： H03D3/24
CPC分类号： H03L7/06 , H03L7/0814 , H03L7/0818 , H03L7/089 , H03L7/093
摘要： A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
摘要翻译：一种用于延迟锁定环路的延迟补偿电路，其包括具有精细延迟线的主延迟线，该延迟线包括精细延迟元件和包括粗延迟元件的粗延迟线，该主延迟线由控制器控制，该延迟补偿电路包括：用于对粗略延迟元件进行建模的可调精细延迟，用于将可调节精细延迟控制为与粗略延迟元件基本相同的值的计数器，用于将系统时钟的表示应用于延迟补偿电路的电路以及从计数器向控制器施加精细延迟计数的电路，用于将主延迟线的精细延迟线调整为与主延迟线的粗略延迟元件基本相同的值。

99. 发明申请

US20110016236A1 APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION 失效
标题翻译：用于生产符合串行互连的混合器件类型的标识符的装置和方法
公开(公告)号：US20110016236A1
公开(公告)日：2011-01-20
申请号：US12892215
申请日：2010-09-28
申请人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM , Shuji SUMI
发明人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM , Shuji SUMI
IPC分类号： G06F13/36
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1063 , G11C7/109
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device. A memory controller can recognize the total number of one DT, in response to the ID received from the last device. In a case of a “don't care” DT is provided to the interconnected devices, IDs are sequentially generated and the total number of the interconnected devices is recognized, regardless of the differences in DTs of the devices.
摘要翻译：混合型的多个存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。响应于从最后一个设备接收的ID，存储器控制器可以识别一个DT的总数。在“不关心”的情况下，将DT提供给互连设备，不管设备的DT的差异如何，顺序地生成ID并且识别互连设备的总数。

100. 发明申请

US20110013455A1 NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE 有权
标题翻译：非易失性存储器串行核心架构
公开(公告)号：US20110013455A1
公开(公告)日：2011-01-20
申请号：US12879566
申请日：2010-09-10
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/04
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G11C5/025 , G11C7/1006 , G11C7/1033 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1072 , G11C7/12 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/32 , G11C2207/107 , G11C2216/14 , G11C2216/20 , G11C2216/30
摘要： A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
摘要翻译：一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。记忆库分为两半，每半部分分为上下扇区。每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。具有集成自列解码电路的共享二维页面缓冲器使每个存储体的电路和芯片面积开销最小化，并且串行数据通道内核减少了通常用于布线宽数据总线的芯片面积。因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

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