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1. 发明授权

US10007439B2 Non-volatile memory serial core architecture 有权
公开(公告)号：US10007439B2
公开(公告)日：2018-06-26
申请号：US15400432
申请日：2017-01-06
申请人： Conversant Intellectual Property Management Inc.
发明人： Jin-Ki Kim
IPC分类号： G06F3/06 , G11C16/26 , G11C16/10 , G11C16/08 , G11C16/32 , G11C16/04
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G11C5/025 , G11C7/1006 , G11C7/1033 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1072 , G11C7/12 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/32 , G11C2207/107 , G11C2216/14 , G11C2216/20 , G11C2216/30
摘要： A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

2. 发明授权

US09881681B2 Semiconductor memory device for storing multivalued data 有权
公开(公告)号：US09881681B2
公开(公告)日：2018-01-30
申请号：US15251798
申请日：2016-08-30
申请人： TOSHIBA MEMORY CORPORATION
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C11/34 , G11C16/34 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

3. 发明授权

US09870831B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US09870831B2
公开(公告)日：2018-01-16
申请号：US15363808
申请日：2016-11-29
申请人： TOSHIBA MEMORY CORPORATION
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/00 , G11C16/34 , G11C7/06 , G11C7/10 , G11C16/10 , G11C16/26 , G06F3/06 , G06F12/02 , G11C16/06 , G11C16/08
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

4. 发明申请

US20170255410A1 MEMORY DEVICE CABLE OF HIGH WRITE EFFICENCY 有权
公开(公告)号：US20170255410A1
公开(公告)日：2017-09-07
申请号：US15346713
申请日：2016-11-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hidehiro SHIGA , Masanobu SHIRAKAWA , Tokumasa HARA
IPC分类号： G06F3/06
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0685 , G11C7/106 , G11C7/1087 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/32 , G11C16/3459 , G11C2216/14
摘要： A memory device includes a first memory string including a first selection transistor and a first memory cell, a second memory string including a second selection transistor and a second memory cell, a bit line electrically connected to the first memory string and the second memory string, and a control circuit configured to perform a collective write operation on the first memory cell and the second memory cell by applying a voltage to turn on the first transistor, a voltage to turn on the second transistor, and then a program voltage at the same time to gates of the first and second memory cells.

5. 发明申请

US20170102977A1 METHOD AND APPARATUS FOR DETERMINING STATUS ELEMENT TOTAL WITH SEQUENTIALLY COUPLED COUNTING STATUS CIRCUITS 审中-公开
公开(公告)号：US20170102977A1
公开(公告)日：2017-04-13
申请号：US15389238
申请日：2016-12-22
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： YIH-SHAN YANG , SHOU-NAN HUNG , CHUN-HSIUNG HUNG , YAO-JEN KUO , MENG-FAN CHANG
IPC分类号： G06F11/07 , G11C16/34 , G11C16/08 , G06F3/06
CPC分类号： G06F11/076 , G06F3/0619 , G06F3/0656 , G06F3/0679 , G06F11/0727 , G06F11/0787 , G06F11/08 , G11C16/08 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/00 , G11C29/022 , G11C29/42 , G11C29/44 , G11C2216/14
摘要： Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.

6. 发明申请

US20170003909A1 MEMORY SYSTEM FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICES THROUGH PLURALITY OF CHANNELS 有权
标题翻译：通过多通道控制半导体存储器件的存储器系统
公开(公告)号：US20170003909A1
公开(公告)日：2017-01-05
申请号：US14957411
申请日：2015-12-02
申请人： SK hynix Inc.
发明人： Sung Yeob CHO
IPC分类号： G06F3/06 , G06F12/08 , G11C16/10
CPC分类号： G06F3/0638 , G06F3/0604 , G06F3/061 , G06F3/0679 , G06F12/0802 , G06F2212/2022 , G06F2212/60 , G06F2212/7203 , G11C7/1006 , G11C16/10 , G11C2216/14
摘要： A memory system includes a plurality of channels; a plurality of semiconductor memory devices connected to the channels; and a controller that controls the semiconductor memory devices through the channels, wherein the controller writes program data in a first semiconductor memory device of the plurality of semiconductor memory devices, and wherein, when the writing of the program data fails, the program data is temporarily stored in a page buffer unit of a second semiconductor memory device of the plurality of semiconductor memory devices connected to a channel other than the channel corresponding to the first semiconductor memory device.
摘要翻译：存储器系统包括多个通道; 连接到所述通道的多个半导体存储器件; 以及控制器，其通过所述通道控制所述半导体存储器件，其中所述控制器将程序数据写入所述多个半导体存储器件的第一半导体存储器件中，并且其中当所述程序数据的写入失败时，所述程序数据是暂时的存储在与除了与第一半导体存储器件相对应的通道之外的通道连接的多个半导体存储器件中的第二半导体存储器件的页面缓冲单元中。

7. 发明授权

US09460804B2 Semiconductor memory device for storing multivalued data 有权
公开(公告)号：US09460804B2
公开(公告)日：2016-10-04
申请号：US14861288
申请日：2015-09-22
申请人： Kabushiki Kaisha Toshiba
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C7/06 , G11C16/34 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

8. 发明申请

US20160012906A1 SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA 有权
公开(公告)号：US20160012906A1
公开(公告)日：2016-01-14
申请号：US14861288
申请日：2015-09-22
申请人： Kabushiki Kaisha Toshiba
发明人： Noboru SHIBATA , Tomoharu TANAKA
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

9. 发明授权

US09177658B2 1T1b and 2T2b flash-based, data-oriented EEPROM design 有权
标题翻译： 1T1b和2T2b闪存为基础，面向数据的EEPROM设计
公开(公告)号：US09177658B2
公开(公告)日：2015-11-03
申请号：US14546294
申请日：2014-11-18
申请人： Peter Wung Lee , Hsing-Ya Tsao
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C11/04 , G11C16/14 , G11C16/34 , G11C16/06 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26
CPC分类号： G11C16/14 , G11C16/0425 , G11C16/0458 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2216/14
摘要： An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.
摘要翻译：提供了一个单晶体管一位（1T1b）基于闪存的EEPROM单元，以及改进的键操作方案，包括施加负字线电压和降低的位线电压用于执行擦除操作，这大大降低了高压应力每个单元用于增强编程/擦除周期，同时减小单元大小。由1T1b闪存的EEPROM单元制成的阵列可以在每个程序周期的半页或全页分割编程和预充电周期下进行操作。在单元阵列中利用由Vdd器件制成的PGM缓冲器进一步节省了硅面积。另外，公开了从1T1b单元得到的双晶体二极管2位（2T2b）EEPROM单元，其额外的单元尺寸减小，但是与1T1b单元相同的编程和擦除操作的优点在于没有处理变化，大大增强了存储密度，卓越的程序/擦除耐久循环，以及在高温环境下运行的能力。

10. 发明授权

US09007850B2 Page buffer, memory device comprising page buffer, and related method of operation 有权
标题翻译：页面缓冲器，包括页面缓冲器的存储器件以及相关的操作方法
公开(公告)号：US09007850B2
公开(公告)日：2015-04-14
申请号：US13718105
申请日：2012-12-18
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Hyun Joo , Il-Han Park , Ki-Hwan Song
IPC分类号： G11C7/10 , G11C11/24 , G11C16/02 , G11C16/10
CPC分类号： G11C11/24 , G11C16/02 , G11C16/10 , G11C2216/14
摘要： A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.
摘要翻译：页面缓冲器包括被配置为存储从外部设备接收的数据的静态锁存器和配置成通过浮动节点接收存储在静态锁存器中的数据的动态锁存器，该动态锁存器包括存储电容器，写入晶体管被配置为写入浮动节点到存储电容器的数据，以及被配置为读取存储电容器的数据的读取晶体管，以及共享浮动节点的写入晶体管和读取晶体管。

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