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1. 发明申请

US20190199360A1 APPARATUSES AND METHODS FOR INDIRECTLY DETECTING PHASE VARIATIONS 审中-公开
公开(公告)号：US20190199360A1
公开(公告)日：2019-06-27
申请号：US16286829
申请日：2019-02-27
申请人： MICRON TECHNOLOGY, INC.
发明人： Hiroki Takahashi
IPC分类号： H03L7/081 , H03L7/091
CPC分类号： H03L7/0812 , H03L7/0816 , H03L7/0818 , H03L7/091
摘要： Apparatuses and methods for indirect phase variation detection are disclosed herein. An example apparatus may include a clock generator circuit comprising a delay-locked loop (DLL) circuit configured to adjust a phase of a clock signal based on a phase of a feedback clock signal during an initial phase-lock operation. The DLL circuit includes a phase deviation detection circuit configured to detect a variation in a phase of the clock signal based on variations in gate delays of an oscillation circuit, and to initiate a subsequent phase-lock operation in response to detecting variations in the gate delays of the oscillation circuit.

2. 发明申请

US20180351560A1 SINGLE-LOCK DELAY LOCKED LOOP WITH CYCLE COUNTER AND METHOD THEREFOR 审中-公开
公开(公告)号：US20180351560A1
公开(公告)日：2018-12-06
申请号：US16059136
申请日：2018-08-09
申请人： Everspin Technologies, Inc.
发明人： Jieming Qi , Aaron Willey
IPC分类号： H03L7/081 , G11C11/16 , H03L7/14
CPC分类号： H03L7/0818 , G11C7/1066 , G11C7/222 , G11C11/1693 , H03L7/0814
摘要： Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.

3. 发明授权

US10014866B2 Clock alignment scheme for data macros of DDR PHY 有权
公开(公告)号：US10014866B2
公开(公告)日：2018-07-03
申请号：US15707205
申请日：2017-09-18
申请人： Invecas, Inc.
发明人： Narasimhan Vasudevan , Venkata N. S. N. Rao , Prasad Chalasani
IPC分类号： H03L7/06 , H03L7/081 , G11C11/4063 , H03L7/083 , G11C7/22 , H03L7/091
CPC分类号： H03L7/0818 , G11C7/222 , G11C11/4063 , G11C11/4076 , H03L7/0812 , H03L7/083 , H03L7/085 , H03L7/089 , H03L7/091
摘要： A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

4. 发明申请

US20170288683A1 COARSE DELAY LOCK ESTIMATION FOR DIGITAL DLL CIRCUITS 审中-公开
公开(公告)号：US20170288683A1
公开(公告)日：2017-10-05
申请号：US15089523
申请日：2016-04-02
申请人： Intel Corporation
发明人： Fangxing Wei , Khushal Chandan , Dan Shi , Michael Allen
IPC分类号： H03L7/081 , G11C11/56 , G11C7/14 , H03L7/091
CPC分类号： H03L7/0814 , G11C7/14 , G11C11/56 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L7/10
摘要： Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

5. 发明申请

US20170214515A1 Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets 有权
公开(公告)号：US20170214515A1
公开(公告)日：2017-07-27
申请号：US15369806
申请日：2016-12-05
申请人： Rambus Inc.
发明人： Hae-Chang Lee , Jared L. Zerbe , Carl William Werner
IPC分类号： H04L7/027 , H03L7/081 , H04L7/00 , H04L7/033 , H03L7/091
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

6. 发明授权

US09490821B2 Glitch less delay circuit for real-time delay adjustments 有权
标题翻译：毛刺更短的延迟电路用于实时延迟调整
公开(公告)号：US09490821B2
公开(公告)日：2016-11-08
申请号：US14497376
申请日：2014-09-26
申请人： Apple Inc.
发明人： Gilbert H. Herbeck , Gregoire J. Le Grand de Mercey , Yair R. Koren , Jung Wan Kim
IPC分类号： H03L7/06 , H03L7/081 , H03K5/01
CPC分类号： H03L7/0818 , H03K5/01 , H03L7/0814
摘要： An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.
摘要翻译：公开了一种装置，其中时钟信号可以通过延迟电路传播。延迟电路可以包括第一和第二延迟级，其中根据对每个延迟级的相应控制信号的值，每个延迟级可以被编程为两个延迟时间中的一个。延迟电路还可以包括可以将相应控制信号的值从第一值改变为第二值的电路。响应于第一级的输出和第二级的输出相等的确定，电路可以改变相应控制信号的值。

7. 发明授权

US09356611B1 Systems and methods involving phase detection with adaptive locking/detection features 有权
公开(公告)号：US09356611B1
公开(公告)日：2016-05-31
申请号：US14607068
申请日：2015-01-27
申请人： GSI Technology, Inc.
发明人： Jyn-Bang Shyu , Yoshinori Sato , Jae Hyeong Kim , Lee-Lean Shu
IPC分类号： H03L7/06 , H03L7/085
CPC分类号： H03L7/085 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/087 , H03L7/095
摘要： Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

8. 发明申请

US20160043861A1 Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets 有权
公开(公告)号：US20160043861A1
公开(公告)日：2016-02-11
申请号：US14820266
申请日：2015-08-06
申请人： Rambus Inc.
发明人： Hae-Chang Lee , Jared L. Zerbe , Carl William Werner
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

9. 发明授权

US09191185B2 Differential bang-bang phase detector using standard digital cells 有权
标题翻译：差分振荡相位检测器采用标准数字单元
公开(公告)号：US09191185B2
公开(公告)日：2015-11-17
申请号：US14268120
申请日：2014-05-02
申请人： QUALCOMM Incorporated
发明人： Jia-yi Chen
IPC分类号： H04L7/00 , H03K3/037 , H03K5/22 , H03L7/081 , H03L7/087 , H04L7/033 , H03L7/085 , H03L7/099
CPC分类号： H04L7/0041 , H03K3/037 , H03K5/22 , H03L7/0816 , H03L7/0818 , H03L7/085 , H03L7/087 , H03L7/0995 , H04L7/0045 , H04L7/0332
摘要： Certain aspects of the present disclosure provide fully differential phase detectors for use in delay-locked loops, for example. One example phase detecting circuit generally includes a first input for a reference signal; a second input for an input signal to be compared with the reference signal; a set-reset (S-R) latch having a set input, a reset input, a first output, and a second output, and a delay (D) flip-flop having a logic input, a clock input, a reset input, and a logic output. The first input is connected with S-R reset input, the second input is connected with S-R set input, the first S-R output is connected with the D clock input, and the second S-R output is connected with the D reset input. The logic output of the D flip-flop indicates whether the input signal is leading or lagging the reference signal.
摘要翻译：本公开的某些方面提供例如用于延迟锁定环路的完全差分相位检测器。一个示例性相位检测电路通常包括用于参考信号的第一输入; 用于与参考信号进行比较的输入信号的第二输入; 具有设定输入，复位输入，第一输出和第二输出的置位复位（SR）锁存器以及具有逻辑输入，时钟输入，复位输入和复位输入的延迟（D）触发器逻辑输出。第一个输入与S-R复位输入相连，第二个输入与S-R设定输入相连，第一个S-R输出与D时钟输入相连，第二个S-R输出与D复位输入相连。 D触发器的逻辑输出指示输入信号是引脚还是滞后参考信号。

10. 发明授权

US09172372B2 Apparatuses, circuits, and methods for reducing metastability in data synchronization 有权
标题翻译：用于减少数据同步中的亚稳态的设备，电路和方法
公开(公告)号：US09172372B2
公开(公告)日：2015-10-27
申请号：US14456263
申请日：2014-08-11
申请人： MICRON TECHNOLOGY, INC.
发明人： Yantao Ma
IPC分类号： H03K19/003 , G11C7/22 , H03L7/081 , G11C7/10 , H03K3/037
CPC分类号： H03K19/00346 , G11C7/1009 , G11C7/222 , H03K3/0375 , H03L7/0814 , H03L7/0816 , H03L7/0818
摘要： Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resin ling from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.
摘要翻译：公开了用于减少或消除数据同步中的亚稳态的意外操作树脂的装置，电路和方法。在一个这样的示例性装置中，采样电路被配置为提供数据输入信号的四个采样。四个样本中的第一和第二样本与锁存信号的第一边缘相关联，并且四个样本中的第三和第四个与锁存信号的第二边缘相关联。屏蔽电路被配置为响应于不共享公共逻辑电平的四个采样来选择性地屏蔽对应于四个采样中的一个采样的信号。屏蔽电路还被配置为响应于选择性地屏蔽或不掩蔽信号来提供决定信号。

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