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91. 发明授权

US09490809B2 Shift register circuit 有权
标题翻译：移位寄存器电路
公开(公告)号：US09490809B2
公开(公告)日：2016-11-08
申请号：US14277918
申请日：2014-05-15
申请人： AU OPTRONICS CORP.
发明人： Wei-Li Lin , Che-Wei Tung , Chia-Heng Chen
IPC分类号： G11C19/00 , H03K19/003 , G11C19/28
CPC分类号： H03K19/00384 , G09G2310/0286 , G11C19/28
摘要： A shift register circuit includes a pull-down circuit, pull-down control circuit, a driving unit, a primary pull-down circuit and a gate driver circuit. The pull-down control circuit is electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit. The a driving unit is electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit. The primary pull-down circuit is electrically connected to the pull-down circuit. The gate driver circuit is electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal. The driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer.
摘要翻译：移位寄存器电路包括下拉电路，下拉控制电路，驱动单元，主下拉电路和栅极驱动器电路。下拉控制电路电连接到下拉电路并且被配置为向下拉电路提供第n级下拉控制信号。驱动单元电连接到下拉控制电路并且被配置为驱动下拉控制电路。主下拉电路电连接到下拉电路。栅极驱动器电路电连接到下拉电路并且被配置为根据第n级控制信号输出第n级栅极驱动信号。驱动单元被配置为接收多个高频时钟信号，并相应地预先使能下拉控制电路，并且n是正整数。

92. 发明授权

US09466254B2 Shift register unit, gate driving circuit and display apparatus 有权
标题翻译：移位寄存器单元，门驱动电路和显示装置
公开(公告)号：US09466254B2
公开(公告)日：2016-10-11
申请号：US14429026
申请日：2014-06-17
申请人： BOE TECHNOLOGY GROUP CO., LTD. , CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Wen Tan , Xiaojing Qi
IPC分类号： G11C19/00 , G09G3/36 , G11C19/28
CPC分类号： G09G3/3677 , G09G3/20 , G09G3/3648 , G09G2300/0426 , G09G2300/0871 , G09G2310/0251 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G11C19/184 , G11C19/28
摘要： A shift register unit, a gate driving circuit and a display apparatus. The shift register unit comprises a bidirectional scan pre-charging module, a pulling-up module, a pulling-down control module, a reset module and a pulling-down module. A connection point where the bidirectional scan pre-charging module and the pulling-up module are connected serves as a pulling-up control node. A connection point where the pulling-down control module and the pulling-down module are connected serves as a pulling-down control node. The pulling-down control module is configured to perform a pulling-down control according to signals inputted from the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal. A bidirectional scanning can be achieved by the bidirectional scan pre-charging module, and the potential at the pulling-up control node and the output signal of the signal output terminal are pulled down to the low level via the pulling-down module, so that the bidirectional pulling-down can be realized. Further, the shift register unit is driven by four clock signal terminals, thus reducing the power consumption of the circuit.
摘要翻译：移位寄存器单元，栅极驱动电路和显示装置。移位寄存器单元包括双向扫描预充电模块，上拉模块，下拉控制模块，复位模块和下拉模块。连接双向扫描预充电模块和上拉模块的连接点作为上拉控制节点。下拉控制模块和下拉模块连接的连接点用作下拉控制节点。下拉控制模块被配置为根据从第二时钟信号端子，第三时钟信号端子和第四时钟信号端子输入的信号执行下拉控制。可以通过双向扫描预充电模块实现双向扫描，并且通过下拉模块将上拉控制节点处的电位和信号输出端子的输出信号下拉到低电平，使得可以实现双向下拉。此外，移位寄存器单元由四个时钟信号端子驱动，从而降低了电路的功耗。

93. 发明授权

US09465756B2 Configurable interconnection system 有权
标题翻译：可配置互连系统
公开(公告)号：US09465756B2
公开(公告)日：2016-10-11
申请号：US12976735
申请日：2010-12-22
申请人： Jon C. R. Bennett
发明人： Jon C. R. Bennett
IPC分类号： G06F13/00 , G06F13/14 , G06F13/36 , G06F13/16 , G11C19/00 , H03K19/17
CPC分类号： G06F13/1684 , G06F13/14 , G06F13/36 , G11C19/00 , H03K19/17 , Y02D10/14
摘要： An interconnection system, apparatus and method is described where the motherboard may be populated with less than all of the modules that it has been designed to accept while maintaining a configuration such that in the event of a module failure, a memory controller failure, or a combination thereof, the connectivity of the remaining modules is maintained. Where data is stored using a RAID organization of the memory on the modules, the data may be reconstructed to a spare module. The system also provides for the orderly incremental expansion of the memory by adding additional memory modules and memory controllers, while maintaining the connectivity properties.
摘要翻译：描述了一种互连系统，装置和方法，其中母板可以被填充少于其被设计为接受的所有模块，同时保持配置，使得在模块故障的情况下，存储器控制器故障或者其组合，保持其余模块的连接性。在使用模块上的存储器的RAID组织存储数据的情况下，可以将数据重建为备用模块。该系统还通过添加额外的内存模块和内存控制器，同时保持连接属性，为内存的有序增量扩展。

94. 发明申请

US20160284309A1 SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS 有权
标题翻译：半导体器件和电子设备
公开(公告)号：US20160284309A1
公开(公告)日：2016-09-29
申请号：US15071948
申请日：2016-03-16
申请人： Synaptics Display Devices GK
发明人： Noriyuki ISHII , Atsushi SHIKATA
IPC分类号： G09G3/36 , G11C19/00
CPC分类号： G09G3/3696 , G09G2330/02
摘要： A semiconductor device has a first mode in which the semiconductor device is used alone and a second mode in which the semiconductor device is used in combination with another semiconductor device. Incase that one driven device is driven using the semiconductor device in the first mode and the second mode, power supply lines are caused to allow electrical conduction to each other outside of each semiconductor device in order to cancel errors of operation power supply voltages of each semiconductor device. In case that a power supply unit of each semiconductor device is operable by receiving an instruction for release of a low power consumption state, a supply start timing of the operation power supply voltages in the second mode is delayed as compared to that in the first mode.
摘要翻译：半导体器件具有其中单独使用半导体器件的第一模式和其中半导体器件与另一半导体器件组合使用的第二模式。在第一模式和第二模式中，使用半导体器件驱动一个驱动器件，使得电源线允许在每个半导体器件的外部彼此导通，以消除每个半导体的工作电源电压的误差设备。在每个半导体器件的电源单元通过接收用于释放低功耗状态的指令来操作的情况下，与第一模式相比，第二模式中的操作电源电压的供应开始定时被延迟。

95. 发明授权

US09437323B2 Shift register circuit for preventing malfunction due to clock skew and memory device including the same 有权
标题翻译：移位寄存器电路，用于防止由于时钟偏移引起的故障和包括其的存储器件
公开(公告)号：US09437323B2
公开(公告)日：2016-09-06
申请号：US14678581
申请日：2015-04-03
申请人： SK hynix Inc.
发明人： Soo-Bin Lim
IPC分类号： G11C8/00 , G11C7/00 , G11C19/00 , G11C19/28 , G11C7/10 , G11C7/22 , G11C16/26 , G11C16/32
CPC分类号： G11C19/00 , G11C7/1066 , G11C7/222 , G11C16/26 , G11C16/32 , G11C19/28 , G11C2029/4402
摘要： A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of latching the output signal of the first latch in synchronization with a second dock having the same skew as the first clock, a second latch capable of latching the output signal of the first flip-flop in synchronization with a third clock having a different skew from the second clock, and a second flip-flop capable of latching the output signal of the second latch circuit in synchronization with a fourth clock having the same skew as the third clock.
摘要翻译：移位寄存器电路可以包括能够与第一时钟同步地锁存输入信号的第一锁存器，能够与第一锁存器的输出信号同步地锁定第一锁存器的第一触发器与具有与第一时钟相同的偏移量的第二基站同步时钟，第二锁存器，其能够与具有与第二时钟不同的偏斜的第三时钟同步地锁存第一触发器的输出信号;以及第二触发器，其能够锁存第二锁存电路的输出信号与第三时钟具有相同偏移的第四时钟同步。

96. 发明授权

US09431074B2 Shiftable memory supporting bimodal storage 有权
标题翻译：支持双模存储的可移动内存
公开(公告)号：US09431074B2
公开(公告)日：2016-08-30
申请号：US14381859
申请日：2012-03-02
申请人： Stavros Harizopoulos , Alkiviadis Simitsis , Harumi Kuno
发明人： Stavros Harizopoulos , Alkiviadis Simitsis , Harumi Kuno
IPC分类号： G06F12/00 , G11C7/10 , G06F17/30 , G06F12/02 , G06F3/06 , G11C19/00 , G11C19/28 , G11C13/00
CPC分类号： G11C7/1036 , G06F3/0608 , G06F12/023 , G06F17/30135 , G06F2212/161 , G06F2212/70 , G11C13/0007 , G11C19/00 , G11C19/28
摘要： A shiftable memory supporting bimodal data storage includes a memory having built-in shifting capability to shift a contiguous subset of data stored in the memory from a first location to a second location within the memory. The shiftable memory further includes a bimodal data storage operator to operate on a data structure comprising the contiguous subset of data words and to provide in-place insertion of a data value using the built-in shifting capability.
摘要翻译：支持双模数据存储器的可移位存储器包括具有内置移位能力的存储器，用于将存储在存储器中的连续数据子集从第一位置移动到存储器内的第二位置。可移动存储器还包括双模数据存储操作器，用于对包括数据字的连续子集的数据结构进行操作，并且使用内置移位能力提供数据值的就地插入。

97. 发明申请

US20160247456A1 PULSE WIDTH MODULATION (PWM) DRIVING SCHEME AND BEZEL REDUCTION 有权
标题翻译：脉冲宽度调制（PWM）驱动方案和减少贝泽
公开(公告)号：US20160247456A1
公开(公告)日：2016-08-25
申请号：US14988594
申请日：2016-01-05
申请人： Apple Inc.
发明人： Hung Sheng Lin , Chin-Wei Lin , Tsung-Ting Tsai , Sang Y. Youn , Hyunwoo Nho
IPC分类号： G09G3/3266 , G11C19/00
CPC分类号： G09G3/3266 , G09G3/2022 , G09G3/2092 , G09G2300/0408 , G09G2310/0286 , G11C19/00
摘要： This application sets forth a circuit configuration for a light emitting diode (LED) or organic light emitting diode (OLED) display. The circuit configuration allows for the pulse-width modulation (PWM) of each emission signal sent to each line of the display. The PWM of each emission signal is accomplished using a gate-in-panel (GIP) controller of the display. The GIP controller uses an arrangement of shift register outputs and a programmable clock input to control an output of an inverter that provides the emission signal. The programmable clock input can be programmed according to a desired timing or duty cycle for the emission signal. In this way, by limiting the duty cycle of the emission signal, dimming and other display features can be exhibited by the LED or OLED display.
摘要翻译：该应用阐述了用于发光二极管（LED）或有机发光二极管（OLED）显示器的电路配置。电路配置允许发送到显示器的每一行的每个发射信号的脉冲宽度调制（PWM）。每个发射信号的PWM通过显示器的面板（GIP）控制器实现。 GIP控制器使用移位寄存器输出和可编程时钟输入的布置来控制提供发射信号的逆变器的输出。可编程时钟输入可根据发射信号所需的定时或占空比进行编程。以这种方式，通过限制发射信号的占空比，LED或OLED显示器可以显示调光和其他显示特征。

98. 发明授权

US09424949B2 Shift register circuit 有权
标题翻译：移位寄存器电路
公开(公告)号：US09424949B2
公开(公告)日：2016-08-23
申请号：US14481183
申请日：2014-09-09
申请人： AU OPTRONICS CORP.
发明人： Kai-Wei Hong , Pin-Yu Chan , Yung-Chih Chen , Li-Wei Liu
IPC分类号： G11C19/00 , G11C19/28 , G11C19/18
CPC分类号： G11C19/28 , G09G2310/0286 , G11C19/186
摘要： A shift register circuit includes a first transistor, a capacitor, a pull-up control circuit, a first pull-down circuit, a pull-down control circuit, a second pull-down circuit and a compensation circuit. The compensation circuit further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. The second transistor, the third transistor, the fourth transistor, and the fifth transistor are corporately used to output a compensation pulse; and the sixth transistor is used to output the compensation pulse to a gate terminal of the first transistor thereby compensating a control signal.
摘要翻译：移位寄存器电路包括第一晶体管，电容器，上拉控制电路，第一下拉电路，下拉控制电路，第二下拉电路和补偿电路。补偿电路还包括第二晶体管，第三晶体管，第四晶体管，第五晶体管和第六晶体管。第二晶体管，第三晶体管，第四晶体管和第五晶体管共同地用于输出补偿脉冲; 并且第六晶体管用于将补偿脉冲输出到第一晶体管的栅极端子，从而补偿控制信号。

99. 发明授权

US09401220B2 Multi-phase gate driver and display panel using the same 有权
标题翻译：多相门驱动器和显示面板使用相同
公开(公告)号：US09401220B2
公开(公告)日：2016-07-26
申请号：US14564692
申请日：2014-12-09
申请人： AU OPTRONICS CORP.
发明人： Chien-Chuan Ko , Meng-Chieh Tsai
IPC分类号： G11C19/00 , G11C19/28 , G09G3/36
CPC分类号： G11C19/287 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , G09G2310/08 , G11C19/00
摘要： A multi-phase gate driver includes a start/end signal generator circuit and X shift register modules. The start/end signal generator circuit is configured to sequentially output N start signals and N end signals according to a first control signal, a second control signal and N groups of clock signals. Each start and end signals have a delay relative to the previous one. Each group of clock signals includes a first clock signal and a second clock signal, which are inverted to each other. The X shift register modules are electrically coupled to the start/end signal generator circuit and each includes N shift register units. The Mth shift register unit of the first shift register module outputs a gate signal according to the Mth group of clock signals, the Mth start signal, and the gate signal outputted from the Mth shift register unit in the second shift register module.
摘要翻译：多相门驱动器包括一个起始/终端信号发生器电路和X个移位寄存器模块。开始/结束信号发生器电路被配置为根据第一控制信号，第二控制信号和N组时钟信号顺序地输出N个起始信号和N个末端信号。每个起始和结束信号相对于前一个信号具有延迟。每组时钟信号包括彼此反相的第一时钟信号和第二时钟信号。 X移位寄存器模块电耦合到起始/结束信号发生器电路，并且每个包括N个移位寄存器单元。第一移位寄存器模块的第M移位寄存器单元根据第M组时钟信号，第M个起始信号和从第二移位寄存器模块中的第M移位寄存器单元输出的门信号输出门信号。

100. 发明申请

US20160203782A1 Array Substrate, Display Panel and Repairing Method Thereof 有权
标题翻译：阵列基板，显示面板及其修复方法
公开(公告)号：US20160203782A1
公开(公告)日：2016-07-14
申请号：US14775371
申请日：2014-11-28
申请人： BOE Technology Group Co., Ltd.
发明人： Hongjun XIE , Kun CAO
IPC分类号： G09G3/36 , G09G3/3266 , G09G3/00 , G11C19/00
CPC分类号： G09G3/3677 , G02F1/1362 , G09G3/006 , G09G3/20 , G09G3/32 , G09G3/3266 , G09G3/36 , G09G2310/021 , G09G2310/0286 , G09G2330/08 , G09G2330/12 , G11C19/00 , H01L27/32
摘要： An array substrate, a display panel and a repairing method thereof are provided. In the array substrate, except the last gate line, both ends of each of the remaining gate lines are provided respectively with first leads connected to the gate line; in each group of gate integrated drive circuits, except a first level shift register, an input terminal of every other shift register is provided with a second lead connected to the input terminal; the first lead connected to one of the gate lines and the second lead connected to an input terminal of the shift register at the next level adjacent thereto have an overlapping area (A) therebetween, and are insulated from each other.
摘要翻译：提供阵列基板，显示面板及其修理方法。在阵列基板中，除了最后的栅极线之外，其余的栅极线的两端分别设置有与栅极线连接的第一引线; 在每组栅极集成驱动电路中，除了第一电平移位寄存器之外，每个其他移位寄存器的输入端子具有连接到输入端子的第二引线; 连接到栅极线之一的第一引线和与其相邻的下一级连接到移位寄存器的输入端的第二引线之间具有重叠区域（A），并且彼此绝缘。

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